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CYK001M16ZCCAU-FVI55 PDF预览

CYK001M16ZCCAU-FVI55

更新时间： 2024-02-22 22:10:18
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路
页数 文件大小 规格书
12页 267K
描述
Pseudo Static RAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48

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CYK001M16ZCCAU-FVI55 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：55 nsJESD-30 代码：R-PBGA-B48
JESD-609代码：e0长度：8 mm
内存密度：16777216 bit内存集成电路类型：PSEUDO STATIC RAM
内存宽度：16功能数量：1
端子数量：48字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-25 °C
组织：1MX16封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：3.3 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：TIN LEAD端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：6 mmBase Number Matches：1

CYK001M16ZCCAU-FVI55 数据手册

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CYK001M16ZCCAU  
MoBL3™  
16-Mbit (1M x 16) Pseudo Static RAM  
Features  
Functional Description  
• Wide voltage range: 2.70V–3.30V  
• Access Time: 55 ns, 70 ns  
• Ultra-low active power  
— Typical active current: 3 mA @ f = 1 MHz  
— Typical active current: 13 mA @ f = fmax  
• Ultra low standby power  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Deep Sleep Mode  
The CYK001M16ZCCAU is a high-performance CMOS  
Pseudo static RAM organized as 1M words by 16 bits that  
supports an asynchronous memory interface. This device  
features advanced circuit design to provide ultra-low active  
current. This is ideal for providing More Battery Life® (MoBL)  
in portable applications such as cellular telephones. The  
device can be put into standby mode when deselected (CE  
HIGH or both BHE and BLE are HIGH). The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE HIGH), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
Writing to the device is accomplished by taking Chip Enables  
(CE LOW) and Write Enable (WE) input LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7), is written into the location specified on the address pins  
(A0 through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
• Offered in a 48-ball BGA Package  
Reading from the device is accomplished by taking Chip  
Enables (CE LOW) and Output Enable (OE) LOW while  
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)  
is LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. Refer to the truth table for a complete description of read  
and write modes.  
This device incorporates a Low Power mode wherein data  
integrity is not guaranteed, but Power Consumption reduces  
to less than 100 µW. This mode (Deep Sleep Mode) is enabled  
by driving ZZ low.See the Truth Table for a complete  
description of Read, Write, and Deep Sleep mode.  
DATA IN DRIVERS  
1M × 16  
Logic Block Diagram  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
RAM Array  
I/O0 – I/O7  
A 3  
I/O8 – I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
ZZ  
Power-Down  
Circuit  
BHE  
BLE  
CE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05454 Rev. *A  
Revised April 21, 2004  
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