Datasheet > CYISM560BSXC

CYISM560BSXC

更新时间： 2024-02-04 14:52:33

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
8页	246K
描述
Clock Generator, 108MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

CYISM560BSXC 技术参数

SM560

Tri-level Logic

With binary logic, four states can be programmed with two

control lines, whereas Tri-level Logic can program nine logic

states using two control lines. Tri-level Logic in the SM560 is

implemented by defining a third logic state in addition to the

standard logic “1” and “0.” Pins 6 and 7 of the SM560

recognize a logic state by the voltage applied to the respective

pin. These states are defined as “0” (Low), “M” (Middle), and

“1” (One). Each of these states has a defined voltage range

that is interpreted by the SM560 as a “0,” “M,” or “1” logic state.

Refer to Table 2 for voltage ranges for each logic state. By

using two equal value resistors (typically 20K) the “M” state

can be easily programmed. Pins 6 or 7 can be tied directly to

ground or VDD for Logic “0” or “1” respectively.

VDD = 3.3 VDC

SM560

20K

1.65 VDC

0 VDC

EX. 1

EX. 2

EX. 3

Figure 1.

Document #: 38-07020 Rev. *E

Page 3 of 8

[+] Feedback

1 234 5 6 7 8

下载PDF

型号	品牌	描述	获取价格	数据表
CYISM560BSXCT	CYPRESS	Clock Generator, 108MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8	获取价格
CYIWOSC1300AA	CYPRESS	1.3 Megapixel CMOS Sensor	获取价格
CYIWOSC3000AA	CYPRESS	3.1 Megapixel CMOS Sensor	获取价格
CYIWOSC3000AA-QYC	CYPRESS	3.1 Megapixel CMOS Sensor	获取价格
CYK001M16SCAU-55BAXI	CYPRESS	16-Mbit (1M x 16) Pseudo Static RAM	获取价格
CYK001M16SCAU-70BAXI	CYPRESS	16-Mbit (1M x 16) Pseudo Static RAM	获取价格