Datasheet > CYISM560BSXC

CYISM560BSXC

更新时间： 2024-02-20 08:07:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
8页	246K
描述
Clock Generator, 108MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8

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CYISM560BSXC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.8
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.889 mm	湿度敏感等级：	1
端子数量：	8	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	108 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	主时钟/晶体标称频率：	108 MHz
认证状态：	COMMERCIAL	座面最大高度：	1.727 mm
最大供电电压：	3.63 V	最小供电电压：	2.97 V
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.8985 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

CYISM560BSXC 数据手册

SM560

Absolute Maximum Ratings^[1]

Supply Voltage (V_DD):.................................... –0.5V to +6.0V

DC Input Voltage:..................................–0.5V to VDD + 0.5V

Junction Temperature .................................–40°C to +140°C

Operating Temperature:...................................... 0°C to 70°C

Storage Temperature.................................. –65°C to +150°C

Static Discharge Voltage (ESD).......................... 2,000V-Min.

Table 2. DC Electrical Characteristics: V_DD= 3.3V, Temp. = 25°C and C_L(Pin 4) = 15 pF, unless otherwise noted

Parameter

V_DD

Description

Power Supply Range

Input High Voltage

Input Middle Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Capacitance

Power Supply Current

Conditions

Min.

2.97

Typ.

3.3

Max.

3.63

V_DD

Unit

±10%

V_INH

V_INM

V_INL

V_OH1

V_OH2

V_OL1

V_OL2

Cin1

Cin2

I_DD1

S0 and S1 only

I_OH= 6 mA

0.85V_DD

V_DD

0.40V_DD0.50V_DD0.60V_DD

0.0

2.4

2.0

0.0

0.15V_DD

I_OH= 20 mA

I_OH= 6 mA

0.4

1.2

I_OH= 20 mA

Xin/CLK (Pin 1)

Xout (Pin 8)

S0, S1, SSCC (Pins 7,6,5)

F_IN= 40 MHz

F_IN= 65 MHz

I_DD2

Table 3. Electrical Timing Characteristics: V_DD= 3.3V, T = 25°C and C_L= 15 pF, unless otherwise noted

Parameter

ICLKFR

Trise

Description

Input Clock Frequency Range

Clock Rise Time (Pin 4)

Clock Fall Time (Pin 4)

Input Clock Duty Cycle

Output Clock Duty Cycle

Cycle-to-Cycle Jitter

Conditions

V_DD= 3.30V

Min.

1.2

Typ.

Max.

108

1.6

Unit

MHz

SSCLK1 @ 0.4 – 2.4V

XIN/CLK (Pin 1)

1.4

Tfall

DTYin

DTYout

JCC

SSCLK1 (Pin 4)

Fin = 25 – 108 MHz

125

175

electronic equipment by the amount of peak energy radiated

from the equipment. By reducing the peak energy at the funda-

mental and harmonic frequencies, the equipment under test is

able to satisfy agency requirements for EMI. Conventional

methods of reducing EMI have been to use shielding, filtering,

multi-layer PCBs, etc. The SM560 uses the approach of

reducing the peak energy in the clock by increasing the clock

bandwidth, and lowering the Q.

SSCG Theory of Operation

The SM560 is a PLL-type clock generator using a proprietary

Cypress design. By precisely controlling the bandwidth of the

output clock, the SM560 becomes a Low EMI clock generator.

The theory and detailed operation of the SM560 will be

discussed in the following sections.

EMI

SSCG

All digital clocks generate unwanted energy in their harmonics.

Conventional digital clocks are square waves with a duty cycle

that is very close to 50%. Because of this 50/50-duty cycle,

digital clocks generate most of their harmonic energy in the

odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to

reduce the amount of energy contained in the fundamental

and odd harmonics by increasing the bandwidth of the funda-

mental clock frequency. Conventional digital clocks have a

very high Q factor, which means that all of the energy at that

frequency is concentrated in a very narrow bandwidth, conse-

SSCG uses a patented technology of modulating the clock

over a very narrow bandwidth and controlled rate of change,

both peak and cycle to cycle. The SM560 takes a narrow band

digital reference clock in the range of 25–108 MHz and

produces a clock that sweeps between a controlled start and

stop frequency and precise rate of change. To understand

what happens to a clock when SSCG is applied, consider a

65-MHz clock with a 50% duty cycle. From a 65-MHz clock we

know the following:

quently, higher energy peaks. Regulatory agencies test

Note:

1. Single Power Supply: The Voltage on any input or I/O pin cannot exceed the power pin during power up.

Document #: 38-07020 Rev. *E

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