Datasheet > CYF0018V_12

CYF0018V_12

更新时间： 2024-01-21 22:31:52

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
30页	697K
描述
18/36/72-Mbit Programmable FIFOs

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数据手册

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CYF0018V_12 数据手册

CYF0018V

CYF0036V

CYF0072V

18/36/72-Mbit Programmable FIFOs

Features

Functional Description

■ Memory organization

❐ Industry’s largest first in first out (FIFO) memory densities:

18 Mbit, 36 Mbit, and 72 Mbit

❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20,

× 24, × 32, × 36

The Cypress programmable FIFO family offers the industry’s

highest-density programmable FIFO memory device. It has

independent read and write ports, which can be clocked up to

133 MHz. User can configure input and output bus sizes. The

maximum bus size of 36 bits enables a maximum data

throughput of 4.8 Gbps. The read and write ports can support

multiple I/O voltage standards. The user-programmable

registers enable user to configure the device operation as

desired. The device also offers a simple and easy-to-use

interface to reduce implementation and debugging efforts,

improve time-to-market, and reduce engineering costs. This

makes it an ideal memory choice for a wide range of applications

including multiprocessor interfaces, video and image

processing, networking and telecommunications, high-speed

data acquisition, or any system that needs buffering at very high

speeds across different clock domains.

■ Up to 133-MHz clock operation

■ Unidirectional operation

■ Independent read and write ports

❐ Supports simultaneous read and write operations

❐ Reads and writes operate on independent clocks, upto a

maximum ratio of two, enabling data buffering across clock

domains.

❐ Supports multiple I/O voltage standard: low voltage

complementary metal oxide semiconductor (LVCMOS) 3.3 V

and 1.8 V voltage standards.

As implied by the name, the functionality of the FIFO is such that

the data is read out of the read port in the same sequence in

which it was written into the write port. The data is sequentially

written into the FIFO from the write port. If the writes and inputs

are enabled, the data on the write port gets written into the device

at the rising edge of the write clock. Enabling the reads and

outputs fetches data on the read port at every rising edge of the

read clock. Both reads and writes can occur simultaneously at

different speeds provided the ratio between read and write clock

is in the range of 0.5 to 2. Appropriate flags are set whenever the

FIFO is empty, full, half-full, almost-full, or almost-empty.

■ Input and output enable control for write mask and read skip

operations

■ Mark and retransmit: resets read pointer to user marked

position

■ Empty, full, half-full, and programmable almost-empty and

almost-full status flags with preselected offsets

■ Flow-through mailbox register to send data from input to output

port, bypassing the FIFO sequence

■ Configure programmable flags and registers through serial or

parallel modes

The device also supports mark and retransmit of data, and a

flow-through mailbox register.

All product features and specs are common to all densities

(CYF0072V, CYF0036V, and CYF0018V) unless otherwise

specified. All descriptions are given assuming the device is

CYF0072V operated in × 36 mode. They hold good for other

densities (CYF0036V, and CYF0018V) and all port sizes × 9,

× 12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.

The only difference will be in the input and output bus width.

Table 1 shows the part of bus with valid data from D[35:0] and

Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and × 36 modes.

■ Separate serial clock (SCLK) input for serial programming

■ Master reset to clear entire FIFO

■ Partial reset to clear data but retain programmable settings

■ Joint test action group (JTAG) port provided for boundary scan

function

■ Industrial temperature range: –40 °C to +85 °C

Cypress Semiconductor Corporation

Document Number: 001-53687 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 16, 2012

12 3 4 5 6 7...30

中文翻译

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与CYF0018V_12相关器件

型号	品牌	获取价格	描述	数据表
CYF0018V_13	CYPRESS	获取价格	18/36/72-Mbit Programmable FIFOs
CYF0018V18L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0018V33L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0018V33L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0036V	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0036V18L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0036V33L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0036V33L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0072V	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0072V18L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO

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