Datasheet > CYF0018V18L-133BGXI

CYF0018V18L-133BGXI

更新时间： 2024-09-24 09:46:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
29页	942K
描述
18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO

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CYF0018V18L-133BGXI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA, BGA209,11X19,40
针数：	209	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.84	最长访问时间：	10 ns
其他特性：	ALSO REQUIRED 1.8V SUPPLY NOM, ALTERNATE MIN MEMORY WIDTH : 9	最大时钟频率 (fCLK)：	133 MHz
周期时间：	7.5 ns	JESD-30 代码：	R-PBGA-B209
JESD-609代码：	e1	长度：	22 mm
内存密度：	18874368 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	209
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX36
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA209,11X19,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	1.5,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.96 mm	子类别：	FIFOs
最大压摆率：	0.6 mA	最大供电电压 (Vsup)：	1.575 V
最小供电电压 (Vsup)：	1.425 V	标称供电电压 (Vsup)：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

CYF0018V18L-133BGXI 数据手册

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CYF0018V, CYF0036V

CYF0072V

18/36/72 Mbit Programmable FIFOs

18/36/72/144 Mbit Programmable FIFOs

Features

Functional Description

■ Memory organization

❐ Industry's largest first in first out (FIFO) memory densities:

18 Mbit, 36 Mbit, and 72 Mbit

❐ Selectable memory organization: ×9, ×12, ×16, ×18, ×20,

×24, ×32, ×36

The Cypress programmable FIFO family offers the industry’s

highest-density programmable FIFO memory device. It has

independent read and write ports, which can be clocked up to

133 MHz. User can configure input and output bus sizes. The

maximum bus size of 36 bits enables a maximum data

throughput of 4.8 Gbps. The read and write ports can support

multiple I/O voltage standards. The user-programmable

registers enable user to configure the device operation as

desired. The device also offers a simple and easy-to-use

interface to reduce implementation and debugging efforts,

improve time-to-market, and reduce engineering costs. This

makes it an ideal memory choice for a wide range of applications

including multiprocessor interfaces, video and image

processing, networking and telecommunications, high-speed

data acquisition, or any system that needs buffering at very high

speeds across different domains.

■ Up to 133-MHz clock operation

■ Unidirectional operation

■ Independent read and write ports

❐ Supports simultaneous read and write operations

❐ Reads and writes operate on independent clocks up to a

maximum ratio of two enabling data buffering across clock

domains

❐ Supports multiple I/O voltage standard: low voltage comple-

mentary metal oxide semiconductor (LVCMOS) 3.3 V

and 1.8 V voltage standards.

As implied by the name, the functionality of the FIFO is such that

the data is read out of the read port in the same sequence in

which it was written into the write port. The data is sequentially

written into the FIFO from the write port. If the writes and inputs

are enabled, the data on the write port gets written into the device

at the rising edge of the write clock. Enabling the reads and

outputs fetches data on the read port at every rising edge of the

read clock. Both reads and writes can occur simultaneously at

different speeds provided the ratio between read and write clock

is in the range of 0.5 to 2. Appropriate flags are set whenever the

FIFO is empty, full, half-full, almost-full, or almost-empty.

■ Input and output enable control for write mask and read skip

operations

■ Mark and retransmit: resets read pointer to user marked

position

■ Empty, full, half-full, and programmable almost-empty and

almost-full status flags with preselected offsets

■ Flow-through mailbox register to send data from input to output

port, bypassing the FIFO sequence

■ Configure programmable flags and registers through serial or

parallel modes

The device also supports mark and retransmit of data, and a

flow-through mailbox register.

All product features and specs are common to all densities (

CYF0072V, CYF0036V, and CYF0018V) unless otherwise

specified. All descriptions are given assuming the device is

CYF0072V operated in ×36 mode. They hold good for other

densities (CYF0036V, and CYF0018V) and all port sizes ×9, ×12,

×16, ×18, ×20, ×24 and ×32 unless otherwise specified. the only

difference will be in the input and output bus width. Table 1 shows

the part of bus with valid data from D[35:0] and Q[35:0] in ×9,

×12, ×16, ×18, ×20, ×24, ×32 and ×36 modes.

■ Separate serial clock (SCLK) input for serial programming

■ Master reset to clear entire FIFO

■ Partial reset to clear data but retain programmable settings

■ Joint test action group (JTAG) port provided for boundary scan

function

■ Industrial temperature range: –40 °C to +85 °C

Cypress Semiconductor Corporation

Document Number: 001-53687 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 31, 2011

12 3 4 5 6 7...29

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CYF0018V18L-133BGXI 替代型号

型号	品牌	替代类型	描述	数据表
CYF0072V18L-133BGXI	CYPRESS	完全替代	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0036V33L-133BGXI	CYPRESS	类似代替	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0072V33L-133BGXI	CYPRESS	功能相似	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO

与CYF0018V18L-133BGXI相关器件

型号	品牌	获取价格	描述	数据表
CYF0018V33L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0018V33L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0036V	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0036V18L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0036V33L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0036V33L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0072V	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0072V18L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0072V18L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0072V25L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209

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