Datasheet > CYF0072V18L-150BGXI

CYF0072V18L-150BGXI

更新时间： 2024-01-30 12:25:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
25页	642K
描述
FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209

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CYF0072V18L-150BGXI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	,
针数：	209	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.83	JESD-30 代码：	R-PBGA-B209
JESD-609代码：	e1	湿度敏感等级：	3
端子数量：	209	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
表面贴装：	YES	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	Base Number Matches：	1

CYF0072V18L-150BGXI 数据手册

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CYFX018VXXX, CYFX036VXXX

CYFX072VXXX, CYFX144VXXX

PRELIMINARY

18/36/72/144 Mbit Programmable FIFOs

Features

Functional Description

■ Memory organization

❐ Industry's largest first in first out (FIFO) memory densities:

18 Mbit, 36 Mbit, 72 Mbit, and 144 Mbit

❐ Selectable memory organization: ×9, ×12, ×16, ×18, ×20,

×24, ×32, ×36

The Cypress programmable FIFO family offers the industry’s

highest-density programmable FIFO memory device. It has

independent read and write ports, which can be clocked up to

150 MHz. You can configure input and output bus sizes. The

maximum bus size of 36 bits enables a maximum data

throughput of 5.4 Gbps. The read and write ports can support

multiple I/O voltage standards. The user-programmable

registers enable you to configure the device operation as

desired. The device also offers a simple and easy-to-use

interface to reduce implementation and debugging efforts,

improve time-to-market, and reduce engineering costs. This

makes it an ideal memory choice for a wide range of applications

including multiprocessor interfaces, video and image

processing, networking and telecommunications, high-speed

data acquisition, or any system that needs buffering at very high

speeds across different domains.

■ Up to 150-MHz clock operation

■ Unidirectional operation

■ Independent read and write ports

❐ Supports simultaneous read and write operations

❐ Reads and writes operate on independent clocks enabling

data buffering across clock domains

❐ Separate input/output (I/O) supply for read and write I/O ports

❐ Selectable I/O voltage standard: supports 3.3 V, 2.5 V,

1.8 V, and 1.5 V voltage standards.

❐ Available in low voltage complementary metal oxide

semiconductor (LVCMOS) and high-speed transceiver logic

(HSTL) one-half I/O standard

As implied by the name, the functionality of the FIFO is such that

the data is read out of the read port in the same sequence in

which it was written into the write port. The data is sequentially

written into the FIFO from the write port. If the writes and inputs

are enabled, the data on the write port gets written into the device

at the rising edge of the write clock. Enabling the reads and

outputs fetches data on the read port at every rising edge of the

read clock. Both reads and writes can occur simultaneously at

different speeds. Appropriate flags are set whenever the FIFO is

empty, full, half-full, almost-full, or almost-empty.

■ Input and output enable control for write mask and read skip

operations

■ User configured multi-queue operating mode

■ Mark and retransmit: resets read pointer to user marked

position

■ Empty, full, half-full, and programmable almost-empty and

almost-full status flags with preselected offsets

The device also supports multi-queue operation, mark and

retransmit of data, and a mailbox register.

■ Mailbox register to send data from input to output port,

bypassing the FIFO sequence

All product features and specs are common to all densities

(CYFX144VXXX, CYFX072VXXX, CYFX036VXXX, and

CYF018VXXX) unless otherwise specified.

■ Configure programmable flags and registers through serial or

parallel modes

■ Separate serial clock (SCLK) input for serial programming

■ Master reset to clear entire FIFO

■ Partial reset to clear data but retain programmable settings

■ Joint test action group (JTAG) port provided for boundary scan

function

■ Industrial temperature range: –40 °C to +85 °C

Cypress Semiconductor Corporation

Document Number: 001-53687 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 6, 2011

12 3 4 5 6 7...25

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与CYF0072V18L-150BGXI相关器件

型号	品牌	获取价格	描述	数据表
CYF0072V25L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0072V33L-110BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0072V33L-133BGXI	CYPRESS	获取价格	18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0072V33L-150BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0144V18L-100BGXI	CYPRESS	获取价格	FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209
CYF0144V18L-133BGXI	CYPRESS	获取价格	FIFO, 4MX36, 10ns, Synchronous, CMOS, PBGA209, FBGA-209
CYF0144V33L-133BGXI	CYPRESS	获取价格	FIFO, 4MX36, 10ns, Synchronous, CMOS, PBGA209, FBGA-209
CYF1018V	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports
CYF1018V_12	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs
CYF1018V18L-100BGXI	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports

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