Datasheet > CYF1036V

CYF1036V

更新时间： 2024-09-25 09:46:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
28页	892K
描述
18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports

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CYF1036V 数据手册

CYF1018V, CYF1036V

CYF1072V

18/36/72-Mbit Programmable

2-Queue FIFOs

18/36/72-Mbit Programmable 2-Queue FIFOs

Features

Functional Description

■ Memory organization

❐ Industry’s largest first in first out (FIFO) memory densities:

18-Mbit, 36-Mbit, 72-Mbit

❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20,

× 24, × 32, × 36

The Cypress programmable FIFO family offers the industry’s

highest-density programmable FIFO memory device. It has

independent read and write ports, which can be clocked up to

100 MHz. User can configure input and output bus sizes. The

maximum bus size of 36 bits enables a maximum data

throughput of 3.6 Gbps. The read and write ports can support

multiple I/O voltage standards. The user-programmable

registers enable user to configure the device operation as

desired. The device also offers a simple and easy-to-use

interface to reduce implementation and debugging efforts,

improve time-to-market, and reduce engineering costs. This

makes it an ideal memory choice for a wide range of applications

including multiprocessor interfaces, video and image

processing, networking and telecommunications, high-speed

data acquisition, or any system that needs buffering at very high

speeds across different domains.

■ Up to 100-MHz clock operation

■ Unidirectional operation

■ Independent read and write ports

❐ Supports simultaneous read and write operations

❐ Reads and writes operate on independent clocks upto a

maximum clock ratio of 2, enabling data buffering across

clock domains

❐ Supports multiple I/O voltage standard: Low voltage

complementary metal oxide semiconductor (LVCMOS) 3.3 V

and 1.8 V voltage standards.

As implied by the name, the functionality of the FIFO is such that

the data is read out of the read port in the same sequence in

which it was written into the write port. The data is sequentially

written into the FIFO from the write port. If the writes and inputs

are enabled, the data on the write port gets written into the device

at the rising edge of the write clock. Enabling the reads and

outputs fetches data on the read port at every rising edge of the

read clock. Both reads and writes can occur simultaneously at

different speeds provided the ratio of read to write clock is

between 0.5 and 2. Appropriate flags are set whenever the FIFO

is empty or full.

■ output enable control for read skip operations

■ User configured two-Queue operating mode

■ Mark and retransmit: resets read pointer to user marked

position

■ Empty and full status flags

■ Flow-through mailbox register to send data from input to output

port, bypassing the FIFO sequence

■ Configure programmable flags and registers through serial or

parallel modes

The device also supports two-Queue operation, mark and

retransmit of data, and a flow-through mailbox register.

■ Separate serial clock (SCLK) input for serial programming

■ Master reset to clear entire FIFO

All product features and specs are common to all densities

(CYF1072V, CYF1036V, and CYF1018V) unless otherwise

specified. All descriptions are given assuming the device is

CYF1072V operated in × 36 mode. They hold good for other

densities (CYF1036V, and CYF1018V) and all port sizes × 9,

×12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.

the only difference will be in the input and output bus width.

Table 1 on page 8 shows the part of bus with valid data from

D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and

× 36 modes.

■ Joint test action group (JTAG) port provided for boundary scan

function

■ Industrial temperature range: –40 °C to +85 °C

Cypress Semiconductor Corporation

Document Number: 001-68321 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 12, 2011

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与CYF1036V相关器件

型号	品牌	获取价格	描述	数据表
CYF1036V18L-100BGXI	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports
CYF1036V33L-100BGXI	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports
CYF1072V	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports
CYF1072V18L-100BGXI	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports
CYF1072V33L-100BGXI	CYPRESS	获取价格	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports
CYF2018V	CYPRESS	获取价格	18/36/72-Mbit Programmable Multi-Queue FIFOs Independent read and write ports
CYF2018V_12	CYPRESS	获取价格	18/36/72-Mbit Programmable Multi-Queue FIFOs
CYF2018V18L-100BGXI	CYPRESS	获取价格	18/36/72-Mbit Programmable Multi-Queue FIFOs Independent read and write ports
CYF2018V33L-100BGXI	CYPRESS	获取价格	18/36/72-Mbit Programmable Multi-Queue FIFOs Independent read and write ports
CYF2036V	CYPRESS	获取价格	18/36/72-Mbit Programmable Multi-Queue FIFOs Independent read and write ports

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