Datasheet > CY8C5568LTI-114T

CY8C5568LTI-114T

更新时间： 2024-01-19 05:45:36

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
111页	2545K
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Micro Peripheral IC

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CY8C5568LTI-114T 数据手册

PSoC^®5: CY8C55 Family Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

With its unique array of configurable blocks, PSoC^®5 is a true system-level solution providing microcontroller unit (MCU), memory,

analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal

processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples

(near DC voltages) to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on

every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including

interfaces such as USB, and multimaster I²C. In addition to communication interfaces, the CY8C55 family has an easy to configure

logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM^®Cortex™-M3 microprocessor core. Designers can

easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a

hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities for analog and digital bill of materials

integration while easily accommodating last minute design changes through simple firmware updates.

❐ Library of advanced peripherals

Features

• Cyclic redundancy check (CRC)

■ 32-bit ARM Cortex-M3 CPU core

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

❐ DC to 67 MHz operation

^❐2^F0^la-^sy^hea^pr^rore^gt^re^an^mtio^mn^e, ^man^od^rym^{, u}u^plti^tp^ole²⁵s⁶ec^Ku^Bri^,ty¹⁰fe⁰a^,0tu⁰r⁰es^{write cycles,}

• Quadrature decoder

■ Analog peripherals (2.7 V  V_DDA 5.5 V)

❐ Up to 64 KB SRAM memory

❐ 128 bytes of cache memory

^❐(²E^-KE^BPR^elO^ecM^tr)^icm^ae^llym^eo^rr^ay^s, ^a1^bm^leill^pio^ron^gc^ry^ac^mle^ms^a, a^bn^led^r2^e0^ady^-e^oaⁿr^ls^yr^me^ete^mn^otio^ryn

❐ 1.024 V ±1% internal voltage reference

❐ Configurable delta-sigma ADC with 8- to 20-bit resolution

• Sample rates up to 192 ksps

• Programmable gain stage: ×0.25 to ×16

^❐A²⁴M^-cB^hA^anhⁿig^eh^l-^dpⁱe^rerf^co^tr^mm^ea^mnc^oe^rybu^as^cc(^eA^sH^sB⁽)^Db^Mu^As⁾a^wcc^ite^hs^ms^ultilayer

• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion

ratio (SINAD), ±1-bit INL/DNL

• Programmable chained descriptors and priorities

• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL

• High bandwidth 32-bit transfer support

■ Low voltage, ultra low power

❐ Two SAR ADCs, each 12-bit at 700 ksps

❐ Four 8-bit 5.5 Msps current IDACs or 1-Msps voltage VDACs

❐ Operating voltage range:2.7 V to 5.5 V

❐ Four comparators with 95-ns response time

❐ 6 mA at 6 MHz

❐ Four uncommitted opamps with 10-mA drive capability

❐ Low power modes including:

^❐c^Fo^on^uf^rig^cu^orⁿa^ftⁱi^go^un^rs^aba^lr^ee^mpr^uo^ltg^ifr^uaⁿm^cm^tioaⁿbl^aeⁿg^aa^loin^ga^bm^lop^cklif^sie^.r^E(^xP^aG^mA^p)^le,

• 2-µA sleep mode

• 300-nA hibernate mode with RAM retention

■ Versatile I/O system

transimpedance amplifier (TIA), mixer, and Sample and Hold

❐ CapSense support

❐ 46 to 70 I/Os (60 GPIOs, 8 SIOs, 2 USBIOs)

❐ Any GPIO to any digital or analog peripheral routability

❐ LCD direct drive from any GPIO, up to 46×16 segments

■ Programming, debug, and trace

^❐i^Snⁱtⁿe^grf^lea^-c^wes^{ire debug (SWD) and single wire viewer (SWV)}

❐ Cortex-M3 flash patch and breakpoint (FPB) block

❐ CapSense^®support from any GPIO^[1]

^❐t^Cra^oc^rte^exin^-Mfo³rm^da^at^ti^aon^{watchpoint and trace (DWT) generates data}

^❐u^Cs^oe^rd^tef^xo^-r^Mp³ri^Inⁿt^sf-^ts^ruty^mle^edⁿe^tab^tu^iogⁿgi^Tn^rg^{ace Macrocell (ITM) can be}

^❐t^Dra^Wce^Ts^ayⁿs^dte^ITm^Ms v^bi^la^octh^kse^cS^oW^mV^mi^unⁿte^icr^afa^tece^{with off-chip debug and}

❐ 1.2 V to 5.5 V I/O interface voltages, up to 4 domains

❐ Maskable, independent IRQ on any pin or port

❐ Schmitt-trigger transistor-transistor logic (TTL) inputs

^❐p^Au^llll^G-u^Pp^I/^Opu^sll^c-^odⁿo^fw^ign^u,^rH^abig^leh-^aZ^s, o^or^pestⁿro^dn^rg^ainou^htp^igu^ht^/low,

❐ 25 mA sink on SIO

■ Digital peripherals

❐ Bootloader programming supportable through I²C, SPI,

UART, USB, and other interfaces

■ Precision, programmable clocking

^❐d²i⁰gi^tt^oal²b⁴lo^pc^rk^os^gr(^aU^mD^mBs^a)^{ble logic device (PLD) based universal}

^❐v³o^tl^ota⁴g⁸e^Mra^Hn^zge^{internal oscillator over full temperature and}

❐ 4- to 25 MHz crystal oscillator for crystal PPM accuracy

❐ Internal PLL clock generation up to 67 MHz

^❐o^Fs^uc^lli^-l^Sla^pto^er^{ed (FS) USB 2.0 12 Mbps using a 24 MHz external}

❐ Four 16-bit configurable timers, counters, and PWM blocks

^❐i⁶m⁷p^Mle^Hm^ze^,n²t⁴fi^-n^biⁱt^te^fii^xm^ep^du^pls^oeⁱⁿr^te^dsⁱp^go^itn^as^le^fil(^tF^erIR^b)^loa^cn^kd⁽i^Dnf^Fin^Bit⁾e^toimpulse

response (IIR) filters

❐ 32.768 kHz watch crystal oscillator

❐ Low power internal oscillator at 1, 33, and 100 kHz

■ Temperature and packaging

❐ –40 °C to +85 °C industrial temperature

❐ 68-pin QFN and 100-pin TQFP package options.

❐ Library of standard peripherals

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• SPI, UART, and I²C

• Many others available in catalog

Notes

1. GPIOs with opamp outputs are not recommended for use with CapSense.

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 001-66235 Rev. *D

Revised February 15, 2012

12 3 4 5 6 7...111

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与CY8C5568LTI-114T相关器件

型号	品牌	描述	获取价格	数据表
CY8C5585AXI-049	CYPRESS	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02	获取价格
CY8C5586AXI-061	CYPRESS	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02	获取价格
CY8C5586LTI-017	CYPRESS	Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68	获取价格
CY8C5587AXI-019	CYPRESS	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02	获取价格
CY8C5587AXI-102	CYPRESS	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02	获取价格
CY8C5587PVI-095	CYPRESS	Multifunction Peripheral, CMOS, PDSO48, 0.300 INCH, SSOP-48	获取价格

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