Datasheet > CY8C5568LTI-114T

CY8C5568LTI-114T

更新时间： 2024-02-04 23:39:37

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
111页	2545K
描述
Micro Peripheral IC

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CY8C5568LTI-114T 数据手册

PSoC^®5: CY8C55 Family Datasheet

1. Architectural Overview

Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit

PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure 1-1. Simplified Block Diagram

Analog Interconnect

Digital Interconnect

System Wide

Resources

Digital System

I2C

Universal Digital Block Array(24 x UDB)

8- Bit

Timer

Quadrature Decoder

16- Bit PRS

Master/

Slave

4- 25 MHz

( Optional)

16- Bit

PWM

UDB

22 

Xtal

Osc

4 x

USB

PHY

UDB

8- Bit

Timer

Counter

FS USB

2.0

UDB

I 2C Slave

UDB

Timer

8- Bit SPI

Logic

12- Bit SPI

UDB

PWM

UDB

IMO

Logic

32.768 KHz

( Optional)

UDB

UART

12- Bit PWM

RTC

Timer

System Bus

Program &

Debug

Memory System

SRAM

CPU System

WDT

and

Wake

8051or

Interrupt

Program

Cortex M3 CPU

Controller

EEPROM

Debug

Trace

PHUB

DMA

FLASH

Cache

ILO

Clocking System

Analog System

Digital

Filter

Block

Power Management

System

LCD Direct

Drive

4 x

ADCs

2 x

Opamp

POR and

LVD

3 per

Opamp

SAR

ADC

4 x SC/CT Blocks

(TIA, PGA, Mixer etc)

Sleep

Power

Temperature

Sensor

4 x

CMP

1.8 V LDO

1 x

Del Sig

ADC

4x DAC

CapSense

Document Number: 001-66235 Rev. *D

Page 3 of 111

1 234 5 6 7...111

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