Datasheet > CY8C5587AXI-019

CY8C5587AXI-019

更新时间： 2024-11-12 07:29:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
102页	2766K
描述
Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, TQFP-100

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CY8C5587AXI-019 数据手册

PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

With its unique array of configurable blocks, PSoC^®5 is a true system-level solution providing microcontroller unit (MCU), memory,

analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal

processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples

(near DC voltages) to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on

every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including

interfaces such as USB, multimaster I²C, and controller area network (CAN). In addition to communication interfaces, the CY8C55

family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM^®Cortex™-M3

microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean

primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities

for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware

updates.

■ Analog peripherals (1.71 V  V_DDA 5.5 V)

Features

❐ 1.024 V ±0.1% internal voltage reference across –40°C to

■ 32-bit ARM Cortex-M3 CPU core

❐ DC to 80 MHz operation

+85°C (14 ppm/°C)

❐ Configurable delta-sigma ADC with 8- to 20-bit resolution

• Sample rates up to 192 ksps

^❐2^F0^la-^sy^hea^pr^rore^gt^re^an^mtio^mn^e, ^man^od^rym^{, u}u^plti^tp^ole²⁵s⁶ec^Ku^Bri^,ty¹⁰fe⁰a^,0tu⁰r⁰es^{write cycles,}

• Programmable gain stage: ×0.25 to ×16

• 12-bit mode, 192 ksps, 70-dB signal-to-noise ratio (SNR),

±1-bit INL/DNL

❐ Up to 64 KB SRAM memory

^❐(²E^-KE^BPR^elO^ecM^tr)^icm^ae^llym^eo^rr^ay^s, ^a1^bm^leill^pio^ron^gc^ry^ac^mle^ms^a, a^bn^led^r2^e0^ady^-e^oaⁿr^ls^yr^me^ete^mn^otio^ryn

• 16-bit mode, 48 ksps, 89-dB SNR, ±2-bit INL, ±1-bit DNL

^❐A²⁴M^-cB^hA^anhⁿig^eh^l-^dpⁱe^rerf^co^tr^mm^ea^mnc^oe^rybu^as^cc(^eA^sH^sB⁽)^Db^Mu^As⁾a^wcc^ite^hs^ms^ultilayer

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

❐ Two SAR ADCs, each 12-bit at 1 Msps^[2]

^❐i⁸m⁰p^-Mle^Hm^ze^,n²t⁴fi^-n^biⁱt^te^fii^xm^ep^du^pls^oeⁱⁿr^te^dsp^igo^itn^as^le^fil(^tF^eI^rR^b)^loa^cn^kd⁽i^Dnf^Fin^Bit⁾e^toimpulse

response (IIR) filters

■ Low voltage, ultra low power

❐ Wide operating voltage range: 0.5 V to 5.5 V

❐ Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs

❐ Four comparators with 95-ns response time

❐ Four uncommitted opamps with 25-mA drive capability

^❐c^Fo^on^uf^rig^cu^orⁿa^ftⁱi^go^un^rs^aba^lr^ee^mpr^uo^ltg^ifr^uaⁿm^cm^tioaⁿbl^aeⁿg^aa^loin^ga^bm^lop^cklif^sie^.r^E(^xP^aG^mA^p)^le,

transimpedance amplifier (TIA), mixer, and Sample and Hold

❐ CapSense support

^❐5^H.ⁱ0^ghV^-eo^fu^fictp^ieuⁿt^{cy boost regulator from 0.5 V input to 1.8 V to}

❐ 2 mA at 6 MHz

❐ Low power modes including:

• 2-µA sleep mode with real time clock (RTC) and

low-voltage detect (LVD) interrupt

■ Programming, debug, and trace

• 300-nA hibernate mode with RAM retention

^❐v^Ji^Te^Aw^Ger⁽⁴(S^wW^irV^e))^,,^sa^en^rd^iaT^{l w}RⁱA^reC^dE^eP^bO^uR^gT^(Sin^Wte^Dr⁾fa⁽c²e^ws^{ire), single wire}

■ Versatile I/O system

❐ 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs)

❐ Any GPIO to any digital or analog peripheral routability

❐ LCD direct drive from any GPIO, up to 46×16 segments

❐ Cortex-M3 flash patch and breakpoint (FPB) block

^❐g^Ce^on^rte^er^xa^-t^Mes³a^En^min^bs^et^dru^dc^et^dio^Tn^rt^ar^ca^ece^Ms^atr^ce^roa^cm^e.^{ll™ (ETM™)}

❐ CapSense^®support from any GPIO^[1]

^❐t^Cra^oc^rte^exin^-Mfo³rm^da^at^ti^aon^{watchpoint and trace (DWT) generates data}

^❐u^Cs^oe^rd^tef^xo^-r^Mp³ri^Inⁿt^sf-^ts^ruty^mle^edⁿe^tab^tu^iogⁿgi^Tn^rg^{ace Macrocell (ITM) can be}

^❐a^Dn^Wd^Tt^,ra^Ec^Te^Ms^,y^asⁿte^dm^ITs^Mv^bia^lot^ch^ke^sS^cW^omV^mo^urⁿT^icR^aA^teC^wEⁱP^thO^oR^ffT^-chipdebug

❐ 1.2 V to 5.5 V I/O interface voltages, up to 4 domains

❐ Maskable, independent IRQ on any pin or port

❐ Schmitt-trigger transistor-transistor logic (TTL) inputs

^❐p^Au^llll^G-u^Pp^I/^Opu^sll^c-^odⁿo^fw^ign^u,^rH^abig^leh-^aZ^s, o^or^pestⁿro^dn^rg^ainou^htp^igu^ht^/low,

❐ Configurable GPIO pin state at power-on reset (POR)

❐ 25 mA sink on SIO

❐ Bootloader programming supportable through I²C, SPI,

UART, USB, and other interfaces

■ Precision, programmable clocking

■ Digital peripherals

^❐d²i⁰gi^tt^oal²b⁴lo^pc^rk^os^gr(^aU^mD^mBs^a)^{ble logic device (PLD) based universal}

^❐v³o^-l^tt^oag⁷e^4-r^Man^Hg^ze^{internal oscillator over full temperature and}

❐ 4- to 33-MHz crystal oscillator for crystal PPM accuracy

❐ Internal PLL clock generation up to 80 MHz

❐ Full CAN 2.0b 16 RX, 8 TX buffers^[2]

❐ Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator

❐ Four 16-bit configurable timers, counters, and PWM blocks

❐ Library of standard peripherals

❐ 32.768-kHz watch crystal oscillator

❐ Low power internal oscillator at 1, 33, and 100 kHz

■ Temperature and packaging

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

❐ –40°C to +85°C degrees industrial temperature

❐ 48-pin SSOP, 68-pin QFN and 100-pin TQFP package

options.

• SPI, UART, and I²C

• Many others available in catalog

❐ Library of advanced peripherals

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

• Quadrature decoder

Notes

1. GPIOs with opamp outputs are not recommended for use with CapSense.

2. This feature on select devices only. See Ordering Information on page 91 for details.

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 001-44094 Rev. *J

Revised September 2, 2010

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与CY8C5587AXI-019相关器件

型号	品牌	获取价格	描述	数据表
CY8C5587AXI-102	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5587PVI-095	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PDSO48, 0.300 INCH, SSOP-48
CY8C5588AXI-020	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5588AXI-022	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5588AXI-060	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5588AXI-060ES0	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5588LTI-0114	CYPRESS	获取价格	Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-220, QFN-68
CY8C5588LTI-052	CYPRESS	获取价格	Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
CY8C5588LTI-114	CYPRESS	获取价格	Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLAINT, MO-220, QFN-68
CY8C5588LTI-114ES0	CYPRESS	获取价格	Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLAINT, MO-220, QFN-68

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