Datasheet > 微控制器和处理器 > 其他 uPs/uCs/外围集成电路> CY8C5568AXI-060T

CY8C5568AXI-060T

更新时间： 2024-02-09 02:52:42

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		多功能外围设备微控制器和处理器时钟
页数	文件大小	规格书
112页	4126K
描述
Micro Peripheral IC

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技术参数
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CY8C5568AXI-060T 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01	风险等级：	5.8
Base Number Matches：	1

CY8C5568AXI-060T 数据手册

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

see 6.2 Power System on page 21. Regulator output not for

external use.

and must be less than or equal to V_DDA. If the I/O pins associated

with V_DDIO0, V_DDIO2or V_DDIO3are not used then that V_DDIO

should be tied to ground (V_SSDor V_SSA).

V_DDA. Supply for all analog peripherals and analog core

regulator. V_DDAmust be the highest voltage present on the

device. All other supply pins must be less than or equal to

XRES. External reset pin. Active low with internal pull-up.

V_DDA

4. CPU

V_DDD. Supply for all digital peripherals and digital core regulator.

_DDDmust be less than or equal to V_DDA

4.1 ARM Cortex-M3 CPU

V_SSA. Ground for all analog peripherals.

The CY8C55 family of devices has an ARM Cortex-M3 CPU

core. The Cortex-M3 is a low-power 32-bit three-stage pipelined

Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is

intended for deeply embedded applications that require fast

interrupt handling features.

V_SSB. Ground connection for boost pump.

V_SSD. Ground for all digital logic and I/O pins.

V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3. Supply for I/O pins. Each

V_DDIOmust be tied to a valid operating voltage (1.71 V to 5.5 V),

Figure 4-1. ARM Cortex-M3 Block Diagram

Data

Watchpoint and

Trace (DWT)

Nested

Interrupt Inputs

Cortex M3 CPU Core

Vectored

Interrupt

Controller

(NVIC)

Embedded

Trace Module

(ETM)

Instrumentation

Trace Module

(ITM)

D-Bus

C-Bus

I-Bus

S-Bus

Trace Pins:

5 for TRACEPORT or

1 for SWV mode

Debug Block

(JTAG and

SWD)

Trace Port

Interface Unit

(TPIU)

JTAG, SWD

Flash Patch

and Breakpoint

(FPB)

Cortex M3 Wrapper

AHB

32 KB

SRAM

Bus

Matrix

Bus

Matrix

256 KB

Flash

Cache

AHB

32 KB

SRAM

Bus

Matrix

AHB Bridge & Bus Matrix

DMA

PHUB

AHB Spokes

Prog.

Digital

Prog.

Analog

Special

Functions

GPIO

Peripherals

The Cortex-M3 CPU subsystem includes these features:

■ ARM Cortex-M3 CPU

Document Number: 001-66235 Rev. **

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与CY8C5568AXI-060T相关器件

型号	品牌	获取价格	描述	数据表
CY8C5568LTI-114	CYPRESS	获取价格	Programmable System-on-Chip (PSoC?)
CY8C5568LTI-114T	CYPRESS	获取价格	Micro Peripheral IC
CY8C5585AXI-049	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5586AXI-061	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5586LTI-017	CYPRESS	获取价格	Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
CY8C5587AXI-019	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5587AXI-102	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5587PVI-095	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PDSO48, 0.300 INCH, SSOP-48
CY8C5588AXI-020	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5588AXI-022	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02

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