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CY8C5568AXI-060T

更新时间： 2024-02-24 16:59:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器时钟
页数 文件大小 规格书
112页 4126K
描述
Micro Peripheral IC

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CY8C5568AXI-060T 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.8
Base Number Matches：1

CY8C5568AXI-060T 数据手册

 浏览型号CY8C5568AXI-060T的Datasheet PDF文件第6页浏览型号CY8C5568AXI-060T的Datasheet PDF文件第7页浏览型号CY8C5568AXI-060T的Datasheet PDF文件第8页浏览型号CY8C5568AXI-060T的Datasheet PDF文件第10页浏览型号CY8C5568AXI-060T的Datasheet PDF文件第11页浏览型号CY8C5568AXI-060T的Datasheet PDF文件第12页 
PRELIMINARY  
PSoC® 5: CY8C55 Family Datasheet  
Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance  
Vssa  
Vssd  
Vdda  
Vddd  
Vssa  
Plane  
Vssd  
Plane  
TCK. JTAG Test Clock programming and debug port connection.  
3. Pin Descriptions  
TDI. JTAG Test Data In programming and debug port  
connection.  
IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for  
high-current DACs (IDAC).  
TDO. JTAG Test Data Out programming and debug port  
connection.  
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High  
current output of uncommitted opamp.[6]  
TMS. JTAG Test Mode Select programming and debug port  
connection.  
Extref0, Extref1. External reference input to the analog system.  
OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to  
uncommitted opamp.  
TRACECLK. Cortex-M3 TRACEPORT connection, clocks  
TRACEDATA pins.  
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting  
input to uncommitted opamp.  
TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections,  
output data.  
GPIO. Provides interfaces to the CPU, digital peripherals,  
analog peripherals, interrupts, LCD segment drive, and  
CapSense.[6]  
SWV. SWV output.  
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.  
May be used as a digital I/O pin; it is powered from VDDD instead  
of from a VDDIO. Pins are Do Not Use (DNU) on devices without  
USB.  
Ind. Inductor connection to boost pump.  
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 KHz crystal oscillator pin.  
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.  
May be used as a digital I/O pin; it is powered from VDDD instead  
of from a VDDIO. Pins are Do Not Use (DNU) on devices without  
USB.  
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator  
pin. If a crystal is not used, then Xi must be shorted to ground  
and Xo must be left floating.  
nTRST. Optional JTAG Test Reset programming and debug port  
connection to reset the JTAG connection.  
V
BOOST. Power sense connection to boost pump.  
BAT. Battery supply to boost pump.  
SIO. Provides interfaces to the CPU, digital peripherals and  
interrupts with a programmable high threshold voltage, analog  
comparator, high sink current, and high impedance state when  
the device is unpowered.  
V
VCCA. Output of analog core regulator and input to analog core.  
Requires a 1 µF capacitor to VSSA. Regulator output not for  
external use.  
SWDCK. SWD Clock programming and debug port connection.  
VCCD. Output of digital core regulator and input to digital core.  
SWDIO. SWD Input and Output programming and debug port  
connection.  
The two VCCD pins must be shorted together, with the trace  
between them as short as possible, and a 1 µF capacitor to VSSD  
;
Notes  
6. GPIOs with opamp outputs are not recommended for use with CapSense.  
Document Number: 001-66235 Rev. **  
Page 9 of 112  
[+] Feedback  
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