PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 2-2. 100-pin TQFP Part Pinout
(TRACEDATA[1], GPIO) P2[5]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
Vddio0
1
2
3
4
5
6
75
74
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
73
72
71
Lines show Vddio
to I/O supply
association
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
P0[0] (GPIO, OpAmp2out)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
70
69
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
7
8
9
68
67
66
65
10
Vssb
Ind
Vboost
Vbat
Vdda
Vssa
11
12
13
14
15
16
17
64
63
Vcca
NC
TQFP
Vssd
XRES
(GPIO) P5[0]
(GPIO) P5[1]
62
61
60
NC
NC
NC
NC
59
58
57
56
55
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
18
19
20
21
22
NC
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO, OpAmp3out)
54
53
52
51
23
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
24
25
P3[6] (GPIO, OpAmp1out)
Figure 2-3 and Figure 2-4 on page 9 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a two-layer board.
■ The two pins labeled VDDD must be connected together.
■ The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-3 and 6.2 Power System on
page 21. The trace between the two VCCD pins should be as short as possible.
■ The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-66235 Rev. **
Page 7 of 112
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