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CY8C27143_13

更新时间： 2024-11-23 12:27:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
64页 1896K
描述
PSoC® Programmable System-on-Chip™

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CY8C27143_13 数据手册

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CY8C27143, CY8C27243  
CY8C27443, CY8C27543  
CY8C27643  
PSoC® Programmable System-on-Chip™  
PSoC® Programmable System-on-Chip™  
Features  
■ Powerful Harvard-architecture processor  
❐ M8C processor speeds up to 24 MHz  
❐ 8 × 8 multiply, 32-bit accumulate  
❐ Low power at high speed  
■ Additional system resources  
❐ I2C slave, master, and multi-master to 400 kHz  
❐ Watchdog and sleep timers  
❐ User-configurable low-voltage detection (LVD)  
❐ Integrated supervisory circuit  
❐ Operating voltage: 3.0 V to 5.25 V  
❐ Operating voltages down to 1.0 V using on-chip switch mode  
❐ On-chip precision voltage reference  
pump (SMP)  
■ Complete development tools  
❐ Industrial temperature range: –40 C to +85 C  
■ Advanced peripherals (PSoC® blocks)  
❐ Twelve rail-to-rail analog PSoC blocks provide:  
• Up to 14-bit analog-to-digital converters (ADCs)  
• Up to 9-bit digital-to-analog converters (DACs)  
• Programmable gain amplifiers (PGAs)  
❐ Free development software (PSoC Designer™)  
❐ Full-featured, in-circuit emulator (ICE) and programmer  
❐ Full-speed emulation  
❐ Complex breakpoint structure  
❐ 128 KB trace memory  
• Programmable filters and comparators  
Logic Block Diagram  
❐ Eight digital PSoC blocks provide:  
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width  
modulators (PWMs)  
Analog  
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0  
Drivers  
• Cyclical redundancy check (CRC) and pseudo random  
sequence (PRS) modules  
PSoC  
CORE  
• Up to two full-duplex universal asynchronous receiver  
transmitters (UARTs)  
System Bus  
• Multiple serial peripheral interface (SPI)masters or slaves  
• Connectable to all general-purpose I/O (GPIO) pins  
❐ Complex peripherals by combining blocks  
Global Digital Interconnect  
Global Analog Interconnect  
SRAM  
SROM Flash 16 KB  
256 Bytes  
■ Precision, programmable clocking  
Sleep and  
Watchdog  
CPU Core (M8C)  
❐ Internal 2.5% 24- / 48-MHz main oscillator  
❐ 24- / 48-MHz with optional 32 kHz crystal  
❐ Optional external oscillator up to 24 MHz  
❐ Internal oscillator for watchdog and sleep  
Interrupt  
Controller  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
■ Flexible on-chip memory  
❐ 16 KB flash program storage 50,000 erase/write cycles  
❐ 256-bytes SRAM data storage  
❐ In-system serial programming (ISSP)  
❐ Partial flash updates  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref.  
Digital  
Block  
Array  
Analog  
Block  
Array  
❐ Flexible protection modes  
Analog  
Input  
Muxing  
❐ Electronically erasable programmable read only memory  
(EEPROM) emulation in flash  
■ Programmable pin configurations  
❐ 25-mA sink, 10-mA source on all GPIOs  
❐ Pull-up, pull-down, high-Z, strong, or open-drain drive modes  
POR and LVD Internal  
Voltage  
Switch  
Mode  
Pump  
on all GPIOs  
Digital  
Clocks  
Multiply  
Accum.  
2
Decimator  
I C  
❐ Eight standard analog inputs on GPIO, plus four additional  
analog inputs with restricted routing  
❐ Four 30-mA analog outputs on GPIOs  
❐ Configurable interrupt on all GPIOs  
System Resets  
Ref.  
SYSTEM RESOURCES  
Cypress Semiconductor Corporation  
Document Number: 38-12012 Rev. *X  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 9, 2013  
1234567...64

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