PSoC™ Mixed Signal Array
Final Data Sheet
CY8C27143, CY8C27243,
CY8C27443, CY8C27543, and CY8C27643
Features
■ Powerful Harvard Architecture Processor
■ M8C Processor Speeds to 24 MHz
■ 8x8 Multiply, 32-Bit Accumulate
■ Low Power at High Speed
■ Precision, Programmable Clocking
■ Internal 2.5% 24/48 MHz Oscillator
■ Additional System Resources
■ I2C™ Slave, Master, and Multi-Master to
■ 24/48 MHz with Optional 32 kHz Crystal
■ Optional External Oscillator, up to 24 MHz
■ Internal Oscillator for Watchdog and Sleep
400 kHz
■ Watchdog and Sleep Timers
■ User-Configurable Low Voltage Detection
■ Integrated Supervisory Circuit
■ On-Chip Precision Voltage Reference
■ 3.0 to 5.25 V Operating Voltage
■ Operating Voltages Down to 1.0V Using On-
■ Flexible On-Chip Memory
Chip Switch Mode Pump (SMP)
■ 16K Bytes Flash Program Storage 50,000
■ Industrial Temperature Range: -40°C to +85°C
Erase/Write Cycles
■ Complete Development Tools
■ Advanced Peripherals (PSoC Blocks)
■ 256 Bytes SRAM Data Storage
■ In-System Serial Programming (ISSP™)
■ Partial Flash Updates
■ Flexible Protection Modes
■ EEPROM Emulation in Flash
■ Free Development Software
■ 12 Rail-to-Rail Analog PSoC Blocks Provide:
(PSoC™ Designer)
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
■ 8 Digital PSoC Blocks Provide:
■ Full-Featured, In-Circuit Emulator and
Programmer
■ Full Speed Emulation
■ Complex Breakpoint Structure
■ 128K Bytes Trace Memory
■ Programmable Pin Configurations
■ 25 mA Sink on all GPIO
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
■ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
■ Up to 12 Analog Inputs on GPIO
■ Four 30 mA Analog Outputs on GPIO
■ Configurable Interrupt on all GPIO
■ Complex Peripherals by Combining Blocks
Analog
Drivers
PSoC™ Functional Overview
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
System Bus
Global Digital Interconnect
SRAM
Global Analog Interconnect
SROM
Flash 16K
256 Bytes
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x43 family can have up to five IO
ports that connect to the global digital and analog interconnects,
providing access to 8 digital blocks and 12 analog blocks.
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Digital
Block
Array
Analog
Block
Array
(2 Rows,
8 Blocks)
(4 Columns,
12 Blocks)
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
POR and LVD Internal
Voltage
Switch
Mode
Pump
Digital
Clocks Accum.
Multiply
I2C
Decimator
System Resets
Ref.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
SYSTEM RESOURCES
August 3, 2004
© Cypress MicroSystems, Inc. 2002 – 2004 — Document No. 38-12012 Rev. *I
1
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