PSoC® Mixed-Signal Array
Final Data Sheet
Automotive:
CY8C27243, CY8C27443, and CY8C27643
Features
■
■
Powerful Harvard Architecture Processor
■
■
Precision, Programmable Clocking
■
Additional System Resources
2
❐
❐
❐
❐
❐
M8C Processor Speeds to 12 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
4.75V to 5.25V Operating Voltage
Extended Temp. Range: -40°C to +105°C
❐
❐
❐
❐
Internal ±4% 24 MHz Oscillator
❐
I C™ Slave, Master, and Multi-Master to
400 kHz
24 MHz with Optional 32.768 kHz Crystal
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
❐
❐
❐
❐
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Flexible On-Chip Memory
Advanced Peripherals (PSoC Blocks)
❐
❐
❐
❐
❐
16K Bytes Flash Program Storage
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
❐
12 Rail-to-Rail Analog PSoC Blocks Provide:
■
Complete Development Tools
❐
Free Development Software
(PSoC™ Designer)
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
Flexible Protection Modes
❐
Full-Featured, In-Circuit Emulator and
Programmer
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
8 Digital PSoC Blocks Provide:
■
Programmable Pin Configurations
❐
❐
❐
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
❐
❐
❐
25 mA Sink on All GPIO
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 12 Analog Inputs on GPIO
Four 30 mA Analog Outputs on GPIO
Configurable Interrupt on All GPIO
❐
❐
❐
❐
Complex Peripherals by Combining Blocks
PSoC® Functional Overview
Analog
Drivers
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
System Bus
Global Digital Interconnect
SRAM
Global Analog Interconnect
SROM
Flash 16K
256 Bytes
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
Multiple Clock Sources
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
device resources to be combined into a complete custom sys-
tem. The CY8C27x43 automotive family can have up to five IO
ports that connect to the global digital and analog interconnects,
providing access to 8 digital blocks and 12 analog blocks.
(IncludesIMO,ILO, PLL, andECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
Digital
Block Array
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum.
2
Decimator
I C
The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture micro-
SYSTEM RESOURCES
November 9, 2006
© Cypress Semiconductor 2004-2006 — Document No. 38-12023 Rev. *D
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