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CY8C27243-12PVXET PDF预览

CY8C27243-12PVXET

更新时间： 2024-11-26 04:53:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器光电二极管时钟
页数 文件大小 规格书
34页 473K
描述
PSoC㈢ Mixed-Signal Array

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CY8C27243-12PVXET 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：0.210 INCH, LEAD FREE, SSOP-20
针数：20Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.72
地址总线宽度：位大小：8
边界扫描：NOCPU系列：M8C
最大时钟频率：24.96 MHz外部数据总线宽度：
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：7.2 mm湿度敏感等级：3
I/O 线路数量：16端子数量：20
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP20,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
RAM（字节）：256RAM（字数）：256
ROM（单词）：16384ROM可编程性：FLASH
座面最大高度：2 mm速度：12 MHz
子类别：Microcontrollers最大压摆率：8 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：5.3 mm
Base Number Matches：1

CY8C27243-12PVXET 数据手册

 浏览型号CY8C27243-12PVXET的Datasheet PDF文件第2页浏览型号CY8C27243-12PVXET的Datasheet PDF文件第3页浏览型号CY8C27243-12PVXET的Datasheet PDF文件第4页浏览型号CY8C27243-12PVXET的Datasheet PDF文件第5页浏览型号CY8C27243-12PVXET的Datasheet PDF文件第6页浏览型号CY8C27243-12PVXET的Datasheet PDF文件第7页 
PSoC® Mixed-Signal Array  
Final Data Sheet  
Automotive:  
CY8C27243, CY8C27443, and CY8C27643  
Features  
■
■
Powerful Harvard Architecture Processor  
■
■
Precision, Programmable Clocking  
■
Additional System Resources  
2
❐
❐
❐
❐
❐
M8C Processor Speeds to 12 MHz  
8x8 Multiply, 32-Bit Accumulate  
Low Power at High Speed  
4.75V to 5.25V Operating Voltage  
Extended Temp. Range: -40°C to +105°C  
❐
❐
❐
❐
Internal ±4% 24 MHz Oscillator  
❐
I C™ Slave, Master, and Multi-Master to  
400 kHz  
24 MHz with Optional 32.768 kHz Crystal  
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
❐
❐
❐
❐
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
On-Chip Precision Voltage Reference  
Flexible On-Chip Memory  
Advanced Peripherals (PSoC Blocks)  
❐
❐
❐
❐
❐
16K Bytes Flash Program Storage  
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
❐
12 Rail-to-Rail Analog PSoC Blocks Provide:  
■
Complete Development Tools  
❐
Free Development Software  
(PSoC™ Designer)  
- Up to 14-Bit ADCs  
- Up to 9-Bit DACs  
Flexible Protection Modes  
❐
Full-Featured, In-Circuit Emulator and  
Programmer  
- Programmable Gain Amplifiers  
- Programmable Filters and Comparators  
8 Digital PSoC Blocks Provide:  
■
Programmable Pin Configurations  
❐
❐
❐
Full Speed Emulation  
Complex Breakpoint Structure  
128K Bytes Trace Memory  
❐
❐
❐
25 mA Sink on All GPIO  
- 8- to 32-Bit Timers, Counters, and PWMs  
- CRC and PRS Modules  
- Up to 2 Full-Duplex UARTs  
- Multiple SPI™ Masters or Slaves  
- Connectable to all GPIO Pins  
Pull Up, Pull Down, High Z, Strong, or Open  
Drain Drive Modes on all GPIO  
Up to 12 Analog Inputs on GPIO  
Four 30 mA Analog Outputs on GPIO  
Configurable Interrupt on All GPIO  
❐
❐
❐
❐
Complex Peripherals by Combining Blocks  
PSoC® Functional Overview  
Analog  
Drivers  
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0  
PSoC  
CORE  
The PSoC® family consists of many Mixed-Signal Array with  
On-Chip Controller devices. These devices are designed to  
replace multiple traditional MCU-based system components  
with one, low cost single-chip programmable device. PSoC  
devices include configurable blocks of analog and digital logic,  
as well as programmable interconnects. This architecture  
allows the user to create customized peripheral configurations  
that match the requirements of each individual application.  
Additionally, a fast CPU, Flash program memory, SRAM data  
memory, and configurable IO are included in a range of conve-  
nient pinouts and packages.  
System Bus  
Global Digital Interconnect  
SRAM  
Global Analog Interconnect  
SROM  
Flash 16K  
256 Bytes  
Sleep and  
Watchdog  
CPUCore(M8C)  
Interrupt  
Controller  
Multiple Clock Sources  
The PSoC architecture, as illustrated on the left, is comprised of  
four main areas: PSoC Core, Digital System, Analog System,  
and System Resources. Configurable global busing allows all  
device resources to be combined into a complete custom sys-  
tem. The CY8C27x43 automotive family can have up to five IO  
ports that connect to the global digital and analog interconnects,  
providing access to 8 digital blocks and 12 analog blocks.  
(IncludesIMO,ILO, PLL, andECO)  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref.  
Analog  
Block  
Array  
Digital  
Block Array  
Analog  
Input  
Muxing  
The PSoC Core  
The PSoC Core is a powerful engine that supports a rich fea-  
ture set. The core includes a CPU, memory, clocks, and config-  
urable GPIO (General Purpose IO).  
POR and LVD  
System Resets  
Internal  
Voltage  
Ref.  
Digital  
Clocks  
Multiply  
Accum.  
2
Decimator  
I C  
The M8C CPU core is a powerful processor with speeds up to  
12 MHz, providing a two MIPS 8-bit Harvard architecture micro-  
SYSTEM RESOURCES  
November 9, 2006  
© Cypress Semiconductor 2004-2006 — Document No. 38-12023 Rev. *D  
1
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中文翻译

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CY8C27243-12PVXET 替代型号

型号 品牌 替代类型 描述 数据表
CY8C27243-12PVXE CYPRESS

完全替代

 PSoC㈢ Mixed-Signal Array
CY8C24223A-12PVXET CYPRESS

完全替代

 PSoC㈢ Mixed-Signal Array
CY8C24223A-12PVXE CYPRESS

完全替代

 PSoC㈢ Mixed-Signal Array

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