PSoC® Mixed-Signal Array
Final Data Sheet
Automotive:
CY8C24223A and CY8C24423A
Features
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■
Powerful Harvard Architecture Processor
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■
Precision, Programmable Clocking
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Additional System Resources
2
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❐
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M8C Processor Speeds to 12 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
4.75V to 5.25V Operating Voltage
Extended Temp. Range: -40°C to +125°C
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❐
Internal ±4% 24 MHz Oscillator
High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
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I C™ Slave, Master, and Multi-Master to
400 kHz
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Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
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Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
Advanced Peripherals (PSoC Blocks)
❐
4K Bytes Flash Program Storage 100 Erase/
Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
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6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
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Complete Development Tools
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Free Development Software
(PSoC Designer™)
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Full-Featured, In-Circuit Emulator and
Programmer
Flexible Protection Modes
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Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
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Programmable Pin Configurations
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25 mA Sink on All GPIO
Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
Up to 10 Analog Inputs on GPIO
Two 30 mA Analog Outputs on GPIO
Configurable Interrupt on All GPIO
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
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Analog
Drivers
PSoC® Functional Overview
Port 2 Port 1 Port 0
PSoC CORE
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
System Bus
Global Digital Interconnect
SRAM
Global Analog Interconnect
Flash 4K
SROM
256 Bytes
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
Multiple Clock Sources
(IncludesIMO,ILO,PLL,andECO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC automotive CY8C24x23A group can have
up to three IO ports that connect to the global digital and analog
interconnects, providing access to 4 digital blocks and 6 analog
blocks.
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Analog
Block
Array
Digital
Block Array
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum .
I2C
Decimator
SYSTEM RESOURCES
October 9, 2006
© Cypress Semiconductor Corp. 2004-2006 — Document No. 38-12029 Rev. *C
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