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CY7C68024-56LFXC PDF预览

CY7C68024-56LFXC

更新时间: 2024-01-21 00:33:25
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 闪存外围集成电路控制器
页数 文件大小 规格书
9页 193K
描述
EZ-USB NX2LP USB 2.0 NAND Flash Controller

CY7C68024-56LFXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:8 X 8 MM, LEAD FREE, MO-220, QFN-56
针数:56Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.75
主机接口标准:USBJESD-30 代码:S-XQCC-N56
JESD-609代码:e3长度:8 mm
湿度敏感等级:3端子数量:56
最高工作温度:70 °C最低工作温度:
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC56,.31SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Bus Controllers
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:8 mm
uPs/uCs/外围集成电路类型:SECONDARY STORAGE CONTROLLER, FLASH MEMORY DRIVEBase Number Matches:1

CY7C68024-56LFXC 数据手册

 浏览型号CY7C68024-56LFXC的Datasheet PDF文件第2页浏览型号CY7C68024-56LFXC的Datasheet PDF文件第3页浏览型号CY7C68024-56LFXC的Datasheet PDF文件第4页浏览型号CY7C68024-56LFXC的Datasheet PDF文件第5页浏览型号CY7C68024-56LFXC的Datasheet PDF文件第6页浏览型号CY7C68024-56LFXC的Datasheet PDF文件第7页 
CY7C68023/CY7C68024  
EZ-USB NX2LP™ USB 2.0 NAND Flash Controller  
• 43-mA Typical Active Current  
1.0  
Features  
• Space-saving and lead-free 56-QFN package (8mm ×  
• High (480-Mbps) or full (12-Mbps) speed USB support  
• Both common NAND page sizes supported  
— 512bytes –Up to 1Gbit Capacity  
— 2K bytes –Up to 8Gbit Capacity  
• 8 chip enable pins  
8mm)  
• Support for board-level manufacturing test via USB  
interface  
• 3.3V NAND Flash operation  
NAND Flash power management support  
— Up to 8 NAND Flash single-device chips  
— Up to 4 NAND Flash dual-device chips  
• Industry standard ECC NAND Flash correction  
— 1-bit per 256 correction  
2.0  
Introduction  
The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND  
Flash controller. This controller adheres to the Mass Storage  
Class Bulk-Only Transport Specification. The USB port of the  
NX2LP is connected to a host computer directly or via the  
downstream port of a USB hub. Host software issues  
commands and data to the NX2LP and receives status and  
data from the NX2LP using standard USB protocol.  
— 2-bit error detection  
• Industry standard (SmartMedia) page management for  
wear leveling algorithm, bad block handling, and Physical  
to Logical management.  
• Supports 8-bit NAND Flash interfaces  
The NX2LP supports industry leading 8-bit NAND Flash inter-  
faces and both common NAND page sizes of 512 and 2k  
bytes. Eight chip enable pins allow the NX2LP to be connected  
to up to eight single- or four dual-device NAND Flash chips.  
• Supports 30ns, 50ns, 100ns NAND Flash timing  
• Complies with USB Mass Storage Class Specification rev  
1.0  
• CY7C68024 complies with USB 2.0 Specification for Bus-  
Powered Devices (TID# 40460274)  
Certain NX2LP features are configurable, enabling the NX2LP  
to meet the needs of different designs’ requirements.  
Write Protect  
LED2#  
Chip Reset  
LED1#  
24 MHz  
PLL  
Xtal  
EZ-USB NX2LP  
Internal Control Logic  
Control  
NAND Control Signals  
Chip Enable Signals  
8-bit Data Bus  
NAND Flash  
Interface  
Logic  
Smart HS/  
FS USB  
Engine  
VBUS  
D+  
D-  
USB 2.0  
Xceiver  
Data  
Figure 1-1. NX2LP Block Diagram  
Cypress Semiconductor Corporation  
Document #: 38-08055 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised March 16, 2005  

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