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CY7C68300B PDF预览

CY7C68300B

更新时间: 2024-02-18 09:15:06
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
36页 457K
描述
EZ-USB AT2LPTM USB 2.0 to ATA/ATAPI Bridge

CY7C68300B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:VQCCN, LCC56,.31SQ,20
针数:56Reach Compliance Code:unknown
风险等级:5.61地址总线宽度:3
总线兼容性:ATA; ATAPI最大时钟频率:24 MHz
外部数据总线宽度:16JESD-30 代码:S-PQCC-N56
JESD-609代码:e0长度:8 mm
湿度敏感等级:3端子数量:56
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:VQCCN
封装等效代码:LCC56,.31SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:0.9906 mm子类别:Bus Controllers
最大压摆率:260 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmuPs/uCs/外围集成电路类型:BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches:1

CY7C68300B 数据手册

 浏览型号CY7C68300B的Datasheet PDF文件第2页浏览型号CY7C68300B的Datasheet PDF文件第3页浏览型号CY7C68300B的Datasheet PDF文件第4页浏览型号CY7C68300B的Datasheet PDF文件第5页浏览型号CY7C68300B的Datasheet PDF文件第6页浏览型号CY7C68300B的Datasheet PDF文件第7页 
CY7C68300B/CY7C68301B  
CY7C68320/CY7C68321  
EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge  
• Support for CompactFlash and one ATA/ATAPI device  
1.0 Features (CY7C68300B/CY7C68301B and  
CY7C68320/CY7C68321)  
• Can place the ATA interface in high-impedance (Hi-Z) to  
allow sharing of the ATA bus with another controller (e.g.,  
an IEEE-1394 to ATA bridge chip or MP3 Decoder)  
• Fixed-function mass storage device—requires no firmware  
code  
• Support for board-level manufacturing test via USB  
interface  
• Two power modes: Self-powered and USB bus-powered to  
enable bus powered CF readers and truly portable USB  
hard drives  
• Low-power 3.3V operation  
• FullycompatiblewithnativeUSBmassstorageclassdrivers  
• Certified compliant for USB 2.0 (TID# 40460273), the USB  
Mass Storage Class, and the USB Mass Storage Class  
Bulk-Only Transport (BOT) Specification  
• Cypress mass storage class drivers available for Windows  
(98SE, ME, 2000, XP) and Mac OS X  
• Operates at high (480-Mbps) or full (12-Mbps) speed USB  
• Complies with ATA/ATAPI-6 specification  
1.1  
Features (CY7C68320/CY7C68321 only)  
• Supports HID interface or custom GPIOs to enable features  
such as single button backup, power-off, LED-based notifi-  
cation, etc.  
• Supports 48-bit addressing for large hard drives  
• Supports ATA security features  
• Supports all ATA commands via ATACB function  
• Supports mode page 5 for BIOS boot support  
• Lead-free 56-pin QFN and 100-pin TQFP packages  
• CY7C68321 is ideal for battery-powered designs  
• CY7C68320 is ideal for self- and bus-powered designs  
• SupportsATAPIserialnumberVPDpageretrievalforDigital  
Rights Management (DRM) compatibility  
• Supports PIO modes 0, 3, 4, multiword DMA mode 2, and  
UDMA modes 2, 3, 4  
1.2  
Features (CY7C68300B/CY7C68301B only)  
• Pin-compatible with CY7C68300A (using Backward  
Compatibility mode)  
• Uses one external serial EEPROM for storage of USB  
descriptors and device configuration data  
• Lead-free 56-pin SSOP and 56-pin QFN packages  
• CY7C68301B is ideal for battery-powered designs  
• CY7C68300B is ideal for self- and bus-powered designs  
• ATA interface IRQ signal support  
• Support for one or two ATA/ATAPI devices  
2.0  
Block Diagram  
SCL  
SDA  
I2C Bus Controller  
Misc control signals  
24  
MHz  
XTAL  
PLL  
ATA_EN (ATA Interface 3-sta  
te)  
Internal Control Logic  
ATA Interface  
Control Signals  
Control  
ATA  
Interf ace  
Logic  
16 Bit ATA Data  
VBUS  
D+  
D-  
CY Smart USB  
FS/HS Engine  
USB 2.0 XCVR  
4kByte FIFO  
Data  
Figure 2-1. Block Diagram  
3901 North First Street  
Cypress Semiconductor Corporation  
Document 38-08033 Rev. *D  
San Jose, CA 95134  
408-943-2600  
Revised February 21, 2005  

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