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CY7C68033_09 PDF预览

CY7C68033_09

更新时间： 2024-11-24 06:51:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 闪存控制器
页数 文件大小 规格书
34页 1292K
描述
EZ-USB NX2LP-Flex Flexible USB NAND Flash Controller

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CY7C68033_09 数据手册

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CY7C68033, CY7C68034  
EZ-USB NX2LP-Flex™ Flexible USB  
NAND Flash Controller  
■ 12 Fully Programmable GPIO Pins  
CY7C68033/CY7C68034 Silicon Features  
■ Integrated, Industry-standard Enhanced 8051  
❐ 48 MHz, 24 MHz, or 12 MHz CPU operation  
❐ Four clocks per instruction cycle  
❐ Three counter/timers  
❐ Expanded interrupt system  
❐ Two data pointers  
■ Certified Compliant for Bus- or Self-powered USB 2.0  
Operation (TID# 40490118)  
■ Single-Chip, Integrated USB 2.0 Transceiver and Smart SIE  
■ Ultra Low Power – 43 mA Typical Current Draw in Any Mode  
■ Enhanced 8051 Core  
❐ Firmware runs from internal RAM, which is downloaded from  
NAND flash at startup  
■ 3.3V Operation with 5V Tolerant Inputs  
■ Vectored USB Interrupts and GPIF/FIFO Interrupts  
❐ No external EEPROM required  
■ Separate Data Buffers for the Setup and Data portions of a  
CONTROL Transfer  
■ 15 KBytes of On-Chip Code/Data RAM  
❐ Default NAND firmware ~8 kB  
❐ Default free space ~7 kB  
■ Integrated I2C Controller, Runs at 100 or 400 kHz  
■ Four Integrated FIFOs  
■ Four Programmable BULK/INTERRUPT/ISOCHRONOUS  
❐ Integrated glue logic and FIFOs lower system cost  
❐ Automatic conversion to and from 16-bit buses  
❐ Master or slave operation  
❐ Uses external clock or asynchronous strobes  
❐ Easy interface to ASIC and DSP ICs  
Endpoints  
❐ Buffering options: double, triple, and quad  
■ Additional Programmable (BULK/INTERRUPT) 64-byte  
Endpoint  
■ SmartMedia Standard Hardware ECC Generation with 1-bit  
Correction and 2-bit Detection  
■ Available in Space Saving, 56-pin QFN Package  
CY7C68034 Only Silicon Features:  
■ GPIF (General Programmable Interface)  
■ Ideal for Battery Powered Applications  
❐ Suspend current: 100 μA (typ)  
❐ Enables direct connection to most parallel interfaces  
❐ Programmable waveform descriptors and configuration  
registers to define waveforms  
❐ Supports multiple Ready (RDY) inputs and Control (CTL)  
outputs  
CY7C68033 Only Silicon Features:  
■ Ideal for Non-battery Powered Applications  
❐ Suspend current: 300 μA (typ)  
High-performance,  
enhanced 8051 core  
with low power options  
24 MHz  
Ext. Xtal  
Logic Block Diagram  
NX2LP-Flex  
/0.5  
/1.0  
/2.0  
8051 Core  
12/24/48 MHz,  
x20  
2
PLL  
I C  
four clocks/cycle  
Master  
V
CC  
Connected for  
full speed USB  
Additional I/Os  
1.5k  
NAND  
Boot Logic  
(ROM)  
GeneralProgrammable  
I/F to ASIC/DSP or bus  
standards such as 8-bit  
GPIF  
NAND, EPP, and so on.  
RDY (2)  
CTL (3)  
USB  
2.0  
XCVR  
D+  
D–  
15 kB  
RAM  
CY  
Smart  
USB  
ECC  
1.1/2.0  
Engine  
Up to 96 MB/s burst rate  
Integrated full- and  
high speed XCVR  
4 kB  
8/16  
FIFO  
‘Soft Configuration’ enables  
easy firmware changes  
FIFO and USB endpoint memory  
(master or slave modes)  
Enhanced USB core  
simplifies 8051 code  
Cypress Semiconductor Corporation  
Document #: 001-04247 Rev *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 03, 2009  
[+] Feedback  
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