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CY7C68033_12 PDF预览

CY7C68033_12

更新时间: 2024-02-11 08:19:42
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 闪存控制器
页数 文件大小 规格书
40页 557K
描述
EZ-USB® NX2LP-Flex™ Flexible USB NAND Flash Controller

CY7C68033_12 数据手册

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CY7C68033/CY7C68034  
EZ-USB® NX2LP-Flex™ Flexible USB  
NAND Flash Controller  
EZ-USB® NX2LP-Flex™ Flexible USB NAND Flash Controller  
Integrated, industry-standard enhanced 8051  
CY7C68033/CY7C68034 Silicon Features  
48-MHz, 24-MHz, or 12-MHz CPU operation  
Four clocks for each instruction cycle  
Three counter/timers  
Certified compliant for bus- or self-powered USB 2.0 operation  
(TID# 40490118)  
Expanded interrupt system  
Two data pointers  
Single-chip, integrated USB 2.0 transceiver and smart SIE  
Ultra low power – 43 mA typical current draw in any mode  
Enhanced 8051 core  
Firmware runs from internal RAM that is downloaded from  
NAND Flash at startup  
3.3-V operation with 5 V tolerant inputs  
Vectored USB interrupts and GPIF/FIFO interrupts  
Separate data buffers for the setup and data portions of a  
control transfer  
No external EEPROM required  
Integrated I2C controller, runs at 100 or 400 kHz  
15 KBytes of on-chip code/data RAM  
Default NAND firmware – 8 kB  
Default free space – 7 kB  
Four integrated FIFOs  
Integrated glue logic and FIFOs lower system cost  
Automatic conversion to and from 16-bit buses  
Master or slave operation  
Four programmable bulk/interrupt/isochronous endpoints  
Buffering options: double, triple, and quad  
Uses external clock or asynchronous strobes  
Easy interface to ASIC and DSP ICs  
Additional programmable (bulk/interrupt) 64-byte endpoint  
SmartMedia standard hardware ECC generation with 1-bit  
correction and 2-bit detection  
Available in space saving 56-pin QFN package  
General programmable interface (GPIF)  
Enables direct connection to most parallel interfaces  
Programmable waveform descriptors and configuration  
registers to define waveforms  
CY7C68034 Only Silicon Features  
Ideal for battery powered applications  
Suspend current: 100 A (typ)  
Supports multiple ready (RDY) inputs and control (CTL)  
outputs  
CY7C68033 Only Silicon Features  
Ideal for non-battery powered applications  
Suspend current: 300 A (typ)  
12 fully programmable general purpose I/O (GPIO) pins  
Logic Block Diagram  
High-performance,  
enhanced 8051 core  
with low power options  
24 MHz  
Ext. Xtal  
NX2LP-Flex  
/0.5  
/1.0  
/2.0  
8051 Core  
x 20  
PLL  
2
12/24/48 MHz,  
I C  
four clocks/cycle  
Master  
V
CC  
Connected for  
full speed USB  
Additional I/Os  
1.5k  
NAND  
Boot Logic  
(ROM)  
GeneralProgrammable  
I/F to ASIC/DSP or bus  
standards such as 8-bit  
GPIF  
NAND, EPP, and so on.  
RDY (2)  
CTL (3)  
USB  
2.0  
XCVR  
D+  
D–  
15 kB  
RAM  
CY  
Smart  
USB  
ECC  
1.1/2.0  
Engine  
Up to 96 MB/s burst rate  
Integrated full- and  
high speed XCVR  
4 kB  
8/16  
FIFO  
‘Soft Configuration’ enables  
easy firmware changes  
FIFO and USB endpoint memory  
(master or slave modes)  
Enhanced USB core  
simplifies 8051 code  
Cypress Semiconductor Corporation  
Document Number: 001-04247 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 6, 2012  

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