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CY7C474-25JC PDF预览

CY7C474-25JC

更新时间： 2024-11-27 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
15页 272K
描述
8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags

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CY7C474-25JC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFJ包装说明：PLASTIC, LCC-32
针数：32Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.31Is Samacsys：N
最长访问时间：25 ns其他特性：RETRANSMIT
最大时钟频率 (fCLK)：28.5 MHz周期时间：35 ns
JESD-30 代码：R-PQCC-J32JESD-609代码：e0
长度：13.97 mm内存密度：294912 bit
内存集成电路类型：OTHER FIFO内存宽度：9
功能数量：1端子数量：32
字数：32768 words字数代码：32000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX9
输出特性：3-STATE可输出：NO
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC32,.5X.6封装形状：RECTANGULAR
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：5 V
认证状态：Not Qualified座面最大高度：3.55 mm
最大待机电流：0.02 A子类别：FIFOs
最大压摆率：0.095 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.43 mmBase Number Matches：1

CY7C474-25JC 数据手册

 浏览型号CY7C474-25JC的Datasheet PDF文件第2页浏览型号CY7C474-25JC的Datasheet PDF文件第3页浏览型号CY7C474-25JC的Datasheet PDF文件第4页浏览型号CY7C474-25JC的Datasheet PDF文件第5页浏览型号CY7C474-25JC的Datasheet PDF文件第6页浏览型号CY7C474-25JC的Datasheet PDF文件第7页 
1CY7C474  
CY7C470  
CY7C472  
CY7C474  
8K x 9 FIFO, 16K x 9 FIFO  
32K x 9 FIFO with Programmable Flags  
offered in 600-mil DIP, PLCC, and LCC packages. Each FIFO  
memory is organized such that the data is read in the same  
Features  
• 8K x 9, 16K x 9, and 32K x 9 FIFO buffer memory  
• Asynchronous read/write  
• High-speed 33.3-MHz read/write independent of  
depth/width  
sequential order that it was written. Three status pins—Emp-  
ty/Full (E/F), Programmable Almost Full/Empty (PAFE), and  
Half Full (HF)—are provided to the user. These pins are de-  
coded to determine one of six states: Empty, Almost Empty,  
Less than Half Full, Greater than Half Full, Almost Full, and  
Full.  
• Low operating power  
— I (max.) = 70 mA  
CC  
The read and write operations may be asynchronous; each  
can occur at a rate of 33.3 MHz. The write operation occurs  
when the write (W) signal goes LOW. Read occurs when read  
(R) goes LOW. The nine data outputs go into a high-imped-  
ance state when R is HIGH.  
• Programmable Almost Full/Empty flag  
• Empty, Almost Empty, Half Full, Almost Full, and Full  
status flags  
• Programmable retransmit  
• Expandable in width  
• 5V ± 10% supply  
The user can store the value of the read pointer for retransmit  
by using the MARK pin. A LOW on the retransmit (RT) input  
causes the FIFO to resend data by resetting the read pointer  
to the value stored in the mark pointer.  
• TTL compatible  
• Three-state outputs  
In the standalone and width expansion configurations, a LOW  
on the retransmit (RT) input causes the FIFO to resend the  
data. With the mark feature, retransmit can start from any word  
in the FIFO.  
• Proprietary 0.8-micron CMOS technology  
Functional Description  
The CYC47X FIFO series consists of high-speed, low-power,  
first-in first-out (FIFO) memories with programmable flags and  
retransmit mark. The CY7C470, CY7C472, and CY7C474 are  
8K, 16K, and 32K words by 9 bits wide, respectively. They are  
The CYC47X series is fabricated using a proprietary 0.8-mi-  
cron N-well CMOS technology. Input ESD protection is greater  
than 2001V and latch-up is prevented by the use of reliable  
layout techniques, guard rings, and a substrate bias generator.  
Logic Block Diagram  
Pin Configurations  
DATAINPUTS  
(D –D )  
DIP  
PLCC/LCC  
Top View  
0
8
Top View  
V
cc  
W
1
28  
D
D
D
D
2
3
4
27  
26  
8
3
2
4
5
6
4
3
2
1
32 31 30  
29  
D
D
D
D
5
6
7
6
D
2
PROGRAMMABLE  
FLAG REGISTER  
28  
27  
7
25  
24  
23  
22  
21  
D
1
NC  
D
D
D
7
5
1
D
0
RT  
8
9
26  
25  
24  
23  
0
6
RT  
7C470  
7C472  
7C474  
7C470  
7C472  
7C474  
MARK  
PAFE  
MR  
E/F  
MARK  
PAFE  
MR  
E/F  
HF  
7
FLAG  
LOGIC  
10  
11  
E/F  
PAFE  
8
Q
0
Q
0
9
HF  
HF  
Q
20  
19  
18  
17  
16  
15  
Q
1
7
Q
1
12  
13  
22  
21  
Q
7
10  
11  
12  
13  
NC  
RAM ARRAY  
8K x 9  
16K x 9  
R
Q
WRITE  
POINTER  
6
Q
6
READ  
POINTER  
Q
2
Q
2
W
RT  
14 15 16 17 18 19 20  
Q
Q
3
8
5
4
MARK  
32K x 9  
Q
Q
R
GND  
14  
7C470–2  
MARK  
POINTER  
7C470–3  
THREE–  
STATE  
BUFFERS  
DATAOUTPUTS  
(Q –Q )  
0
8
MR  
RESET  
LOGIC  
7C470–1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
December 1990 – Revised April 1995  
1234567...15

中文翻译

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 		8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags
CY7C474-25JIR CYPRESS

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 		FIFO, 32KX9, 25ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32
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CY7C474-25LMB CYPRESS

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 		8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags
CY7C474-25PC CYPRESS

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 		8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags
CY7C474-25PI CYPRESS

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 		FIFO, 32KX9, 25ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
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CY7C474-40DI CYPRESS

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 		FIFO, 32KX9, 40ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C474-40DMB CYPRESS

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 		8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags
CY7C474-40JC CYPRESS

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 		8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags

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