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CY7C4804V25-166BBC PDF预览

CY7C4804V25-166BBC

更新时间: 2024-11-29 19:54:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
30页 375K
描述
FIFO, 4KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, BGA-288

CY7C4804V25-166BBC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:19 X 19 MM, 1 MM PITCH, BGA-288
针数:288Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:4 ns
其他特性:RETRANSMIT最大时钟频率 (fCLK):166 MHz
周期时间:6 nsJESD-30 代码:S-PBGA-B288
JESD-609代码:e0长度:19 mm
内存密度:327680 bit内存集成电路类型:OTHER FIFO
内存宽度:80功能数量:1
端子数量:288字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX80可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA288,18X18,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
电源:1.5,2.5 V认证状态:Not Qualified
座面最大高度:1.4 mm最大待机电流:0.01 A
子类别:FIFOs最大压摆率:0.25 mA
最大供电电压 (Vsup):2.6 V最小供电电压 (Vsup):2.4 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:19 mmBase Number Matches:1

CY7C4804V25-166BBC 数据手册

 浏览型号CY7C4804V25-166BBC的Datasheet PDF文件第2页浏览型号CY7C4804V25-166BBC的Datasheet PDF文件第3页浏览型号CY7C4804V25-166BBC的Datasheet PDF文件第4页浏览型号CY7C4804V25-166BBC的Datasheet PDF文件第5页浏览型号CY7C4804V25-166BBC的Datasheet PDF文件第6页浏览型号CY7C4804V25-166BBC的Datasheet PDF文件第7页 
CY7C4808V25  
CY7C4806V25  
CY7C4804V25  
sure  
C025/0251  
PRELIMINARY  
2.5V 4K/16K/64K x 80 Unidirectional  
Synchronous FIFO with Bus Matching  
• Bus matching on both ports: ×80, ×40, ×20, ×10  
Features  
• Free-running CLKA and CLKB. Clocks may be asyn-  
chronous or coincident  
• Cypress standard or First-Word Fall-Through modes  
• Serial and parallel programming of Almost Empty/Full  
flags, each with three default values (8, 16, 64)  
• High-speed, low-power, unidirectional,  
First-in First-out (FIFO) memories with bus-matching  
capabilities  
• 64K × 80 (CY7C4808V25)  
• 16K × 80 (CY7C4806V25)  
• 4K × 80 (CY7C4804V25)  
• 2.5V ± 100 mV power supply  
• All I/Os are 1.5V HSTL  
• Master and partial reset capability  
• Retransmit capability  
• Big or Little Endian format  
• 288FBGA19mm×19mm(1.0-mmballpitch)packaging  
• Width and depth expansion capability  
• Fabricated using Cypress 0.21-micron CMOS technol-  
ogy for optimum speed/power  
• Individual clock frequency up to 200 MHz (5-ns  
Read/Write cycle times)  
• High-speed access with tA = 3.8 ns  
Preliminary Top-level Block Diagram  
CLKA  
CSA  
CLKB  
CSB  
ENB  
BE/FWFT  
SIZE1B  
SIZE2B  
RT/SPM  
Port A  
ENA  
Control  
Port B  
Control  
Logic  
Logic  
SIZE1A  
SIZE2A  
4K/16K/64K×80  
OE  
Dual-ported  
Memory Array  
80  
A
790  
80  
B
790  
Read  
Pointer  
Write  
Pointer  
MR  
PR  
FIFO  
Reset  
Logic  
Status  
Flag Logic  
FF/IR  
AF  
EF/OR  
AE  
TDO  
Programmable Flag  
Offset Registers  
FS0/SD  
FS1/SEN  
JTAG Controller  
TDI TCK TMS TRST  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06028 Rev. *B  
Revised December 26, 2002  

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