Datasheet > 存储 > FIFO> CY7C4801-35AC

CY7C4801-35AC

更新时间： 2024-11-27 04:53:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
23页	286K
描述
256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs

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CY7C4801-35AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	PLASTIC, TQFP-64
针数：	64	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.74	最长访问时间：	20 ns
最大时钟频率 (fCLK)：	28.6 MHz	周期时间：	35 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	14 mm	内存密度：	2304 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	9
功能数量：	1	端子数量：	64
字数：	256 words	字数代码：	256
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256X9
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP64,.66SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.1 A	子类别：	FIFOs
最大压摆率：	0.1 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

CY7C4801-35AC 数据手册

CY7C4831/4

CY7C4801/4811/4821

CY7C4831/4841/4851

256/512/1K/2K/4K/8K x9 x2

Double Sync FIFOs

These FIFOs have two independent sets of 9-bit input and

output ports that are controlled by separate clock and enable

signals. The input port is controlled by a free-running clock

(WCLKA,WCLKB) and two write-enable pins (WENA1,

WENA2/LDA, WENB1, WENB2/LDB).

Features

• Double high speed, low power, first-in first-out (FIFO)

memories

• Double 256 x 9 (CY7C4801)

• Double 512 x 9 (CY7C4811)

• Double 1K x 9 (CY7C4821)

• Double 2K x 9 (CY7C4831)

• Double 4K x 9 (CY7C4841)

• Double 8K x 9 (CY7C4851)

• Functionally equivalent to two CY7C4201/4211/4221/

4231/4241/4251 FIFOs in a single package

• 0.65 micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10 ns read/write cycle

times)

• Offers optimal combination of large capacity, high

speed, design flexibility, and small footprint

• Fully asynchronous and simultaneous read and write

operation

• Four status flags per device: Empty, Full, and program-

mable Almost Empty/Almost Full

When (WENA1,WENB1) is LOW and (WENA2/LDA,

WENB2/LDB) is HIGH, data is written into the FIFO on the

rising edge of the (WCLKA,WCLKB) signal. While (WENA1,

WENA2/LDA, WENB1, WENB2/LDB) is held active, data is

continually written into the FIFO on each WCLKA, WCLKB

cycle. The output port is controlled in a similar manner by a

free-running read clock (RCLKA, RCLKB) and two read-en-

able pins ((RENA1,RENB1), (RENA2,RENB2)). In addition,

the CY7C48X1 has output enable pins (OEA, OEB) for each

FIFO. The read (RCLKA, RCLKB) and write (WCLKA,

WCLKB) clocks may be tied together for single-clock operation

or the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 100 MHz are

achievable.

Depth expansion is possible using one enable input for system

control, while the other enable is controlled by expansion logic

to direct the flow of data.

• Low power — I_CC1= 60mA

• Output Enable (OEA/OEB) pins

• Depth Expansion Capability

• Width Expansion Capability

• Space-saving 64-pin TQFP

The CY7C48X1 provides twosets of four different statuspins: Empty,

Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags

are programmable to single word granularity. The programmable

flags default to Empty+7 and Full–7.

The flags are synchronous, i.e., they change state relative to

either the read clock (RCLKA,RCLKB) or the write clock

(WCLKA,WCLKB). When entering or exiting the Empty and

Almost Empty states, the flags are updated exclusively by the

(RCLKA,RCLKB). The flags denoting Almost Full, and Full

states are updated exclusively by (WCLKA,WCLKB) The syn-

chronous flag architecture guarantees that the flags maintain

their status for at least one cycle

• PincompatibleandfunctionallyequivalenttoIDT72801,

72811, 72821, 72831, 72841,72851

Functional Description

The CY7C48X1 are Double high-speed, low-power, first-in

first-out (FIFO) memories with clocked read and write interfac-

es. All are 9 bits wide and operate as two separate FIFOs. The

CY7C48X1 are pin-compatible to IDT728X1. Programmable

features include Almost Full/Almost Empty flags. These FIFOs

provide solutions for a wide variety of data buffering needs,

including high-speed data acquisition, multiprocessor interfac-

es, and communications buffering.

All configurations are fabricated using an advanced 0.65µ

N-Well CMOS technology. Input ESD protection is greater than

2001V, and latch-up is prevented by the use of guard rings.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06005 Rev. **

Revised January 15, 1997

12 3 4 5 6 7...23

中文翻译

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与CY7C4801-35AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C4801-35ACT	CYPRESS	获取价格	FIFO, 256X9, 20ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
CY7C4801-35AI	CYPRESS	获取价格	256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs
CY7C4804V25-166BBC	CYPRESS	获取价格	FIFO, 4KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, BGA-288
CY7C4804V25-166C	CYPRESS	获取价格	FIFO, 4KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, FBGA-288
CY7C4804V25-166I	CYPRESS	获取价格	FIFO, 4KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, FBGA-288
CY7C4804V25-200BBC	CYPRESS	获取价格	FIFO, 4KX80, 3.8ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, BGA-288
CY7C4806V25-166BBC	CYPRESS	获取价格	FIFO, 16KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, BGA-288
CY7C4806V25-166C	CYPRESS	获取价格	FIFO, 16KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, FBGA-288
CY7C4806V25-200C	CYPRESS	获取价格	FIFO, 16KX80, 3.5ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, FBGA-288
CY7C4808V25-166BBC	CYPRESS	获取价格	FIFO, 64KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, BGA-288

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