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CY7C43683AV PDF预览

CY7C43683AV

更新时间: 2024-11-23 21:54:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
28页 482K
描述
3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

CY7C43683AV 数据手册

 浏览型号CY7C43683AV的Datasheet PDF文件第2页浏览型号CY7C43683AV的Datasheet PDF文件第3页浏览型号CY7C43683AV的Datasheet PDF文件第4页浏览型号CY7C43683AV的Datasheet PDF文件第5页浏览型号CY7C43683AV的Datasheet PDF文件第6页浏览型号CY7C43683AV的Datasheet PDF文件第7页 
CY7C43663AV  
CY7C43643AV  
CY7C43683AV  
3.3V 1K/4K/16K x36 Unidirectional Synchronous  
FIFO with Bus Matching  
— ICC = 60 mA  
Features  
— ISB = 10 mA  
• High-speed, low-power, unidirectional, First-In  
First-Out (FIFO) memories with bus-matching capabil-  
ities  
• Fully asynchronous and simultaneous Read and Write  
operation permitted  
• Mailbox bypass register for each FIFO  
• 1K × 36 (CY7C43643AV)  
• Parallel and serial programmable Almost Full and  
Almost Empty flags  
• Retransmit function  
• Standard or FWFT user selectable mode  
• Partial reset  
• 4K × 36 (CY7C43663AV)  
• 16K × 36 (CY7C43683AV)  
• 0.25-micron CMOS for optimum speed/power  
• High-speed 133-MHz operation (7.5-ns Read/Write  
cycle times)  
• Big or Little Endian format for word or byte bus sizes  
• 128-pin TQFP packaging  
• Low power  
• Easily expandable in width and depth  
Logic Block Diagram  
MBF1  
CLKA  
Mail1  
Register  
CSA  
Port A  
Control  
Logic  
W/RA  
ENA  
MBA  
RT  
CLKB  
CSB  
1K/4K/16K  
× 36  
Dual Ported  
Memory  
Port B  
Control  
Logic  
W/RB  
ENB  
MBB  
BM  
SIZE  
FIFO,  
Mail1  
Mail2  
Reset  
Logic  
MRS1  
MRS2  
Write  
Pointer  
Read  
Pointer  
PRS  
FF/IR  
AF  
EF/OR  
AE  
Status  
Flag Logic  
36  
B
035  
SPM  
FS0/SD  
FS1/SEN  
Timing  
Mode  
Programmable  
Flag Offset  
Registers  
BE/FWFT  
36  
A
035  
Mail2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06024 Rev. *C  
Revised December 26, 2002  

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