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CY7C43684-7AC PDF预览

CY7C43684-7AC

更新时间: 2024-11-27 04:53:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
39页 646K
描述
1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

CY7C43684-7AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP128,.63X.87,20
针数:128Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.9最长访问时间:6 ns
其他特性:MAILBOX最大时钟频率 (fCLK):133 MHz
周期时间:7.5 nsJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
内存密度:589824 bit内存集成电路类型:BI-DIRECTIONAL FIFO
内存宽度:36功能数量:1
端子数量:128字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.01 A
子类别:FIFOs最大压摆率:0.1 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mm

CY7C43684-7AC 数据手册

 浏览型号CY7C43684-7AC的Datasheet PDF文件第2页浏览型号CY7C43684-7AC的Datasheet PDF文件第3页浏览型号CY7C43684-7AC的Datasheet PDF文件第4页浏览型号CY7C43684-7AC的Datasheet PDF文件第5页浏览型号CY7C43684-7AC的Datasheet PDF文件第6页浏览型号CY7C43684-7AC的Datasheet PDF文件第7页 
CY7C43644  
CY7C43664  
CY7C43684  
1K/4K x36 x2 Bidirectional Synchronous  
FIFO with Bus Matching  
• Fully asynchronous and simultaneous read and write  
operation permitted  
Features  
• High-speed,low-power,bidirectional,First-In,First-Out  
(FIFO) memories with bus matching capabilities  
• 1K x36 x2 (CY7C43644)  
• Mailbox bypass register for each FIFO  
• Parallel and Serial Programmable Almost-Full and  
Almost-Empty flags  
• 4K x36 x2 (CY7C43664)  
• Retransmit function  
• 16K x36 x2 (CY7C43684)  
• 0.35-micron CMOS for optimum speed/power  
• Standard or FWFT mode user selectable  
• Partial Reset  
• High-speed 133-MHz operation (7.5 ns read/write  
cycle times)  
• Low power  
— ICC = 100 mA  
— ISB = 10 mA  
• Big or Little Endian format for word or byte bus sizes  
• 128-pin TQFP packaging  
• Easily expandable in width and depth  
Logic Block Diagram  
MBF1  
CLKA  
Mail 1  
Register  
CSA  
Port A  
Control  
Logic  
CLKB  
CSB  
W/RA  
ENA  
MBA  
RT2  
1K/4K/16K  
x36  
Dual Ported  
W/RB  
Port B  
Control  
Logic  
ENB  
MBB  
Memory  
RTI  
BE  
BM  
SIZE  
MRS1  
PRS1  
FIFO1,  
Mail 1  
Reset  
Logic  
Write  
Pointer  
Read  
Pointer  
FFA/IRA  
AFA  
Status  
Flag Logic  
EFB/ORB  
AEB  
36  
SPM  
FS0/SD  
FS1/SEN  
B
035  
Timing  
Mode  
Programmable  
Flag Offset  
Registers  
BE/FWFT  
36  
A
035  
Status  
Flag Logic  
FFB/IRB  
AFB  
EFA/ORA  
AEA  
Write  
Pointer  
Read  
Pointer  
FIFO1,  
Mail 1  
Reset  
Logic  
MRS2  
PRS2  
256/512/1K  
4K/16K x36  
Dual Ported  
Memory  
Mail 2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06022 Rev. *B  
Revised December 26, 2002  

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