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CY7C43686AV-15AC PDF预览

CY7C43686AV-15AC

更新时间: 2024-11-23 22:20:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
40页 645K
描述
3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO

CY7C43686AV-15AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP128,.63X.87,20
针数:128Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.88最长访问时间:10 ns
其他特性:MAILBOX最大时钟频率 (fCLK):67 MHz
周期时间:15 nsJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
内存密度:589824 bit内存集成电路类型:BI-DIRECTIONAL FIFO
内存宽度:36功能数量:1
端子数量:128字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.012 A子类别:FIFOs
最大压摆率:0.06 mA最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY7C43686AV-15AC 数据手册

 浏览型号CY7C43686AV-15AC的Datasheet PDF文件第2页浏览型号CY7C43686AV-15AC的Datasheet PDF文件第3页浏览型号CY7C43686AV-15AC的Datasheet PDF文件第4页浏览型号CY7C43686AV-15AC的Datasheet PDF文件第5页浏览型号CY7C43686AV-15AC的Datasheet PDF文件第6页浏览型号CY7C43686AV-15AC的Datasheet PDF文件第7页 
3686AV  
CY7C43646AV  
CY7C43666AV  
CY7C43686AV  
3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO  
• Fully asynchronous and simultaneous Read and Write  
operation permitted  
Features  
• 3.3V high-speed, low-power, First-In First-Out (FIFO)  
memories with three independent ports (one bidirec-  
tional ×36, and two unidirectional ×18)  
• 1K ×36/×18×2 (CY7C43646AV)  
• 4K ×36/×18×2 (CY7C43666AV)  
• 16K ×36/×18×2 (CY7C43686AV)  
• 0.25-micron CMOS for optimum speed/power  
• High-speed 133-MHz operation (7.5-ns Read/Write  
cycle times)  
• Low power  
— ICC= 60 mA  
— ISB= 10 mA  
• Mailbox bypass register for each FIFO  
• Parallel and serial programmable Almost Full and  
Almost Empty flags  
• Retransmit function  
• Standard or FWFT user-selectable mode  
• Partial and master reset  
• Big or Little Endian format for word or byte bus sizes  
• 128-pin TQFP packaging  
• Easily expandable in width and depth  
Logic Block Diagram  
MBF1  
CLKA  
Mail1  
Register  
CSA  
W/RA  
ENA  
MBA  
RT2  
Port A  
Control  
Logic  
B
1K/4K/16K  
× 36  
Dual Ported  
Memory  
(FIFO1)  
017  
CLKB  
RENB  
Port B  
Control  
CSB  
Logic  
SIZEB  
MBB  
RTI  
MRS1  
PRS1  
FIFO1,  
Mail1  
Reset  
Logic  
Write  
Pointer  
Read  
Pointer  
FFA/IRA  
AFA  
Status  
Flag Logic  
EFB/ORB  
AEB  
Common  
Port Logic  
(B and C)  
SPM  
FS0/SD  
FS1/SEN  
Timing  
Mode  
Programmable  
Flag Offset  
Registers  
BE/FWFT  
A
035  
Status  
Flag Logic  
FFC/IRC  
AFC  
EFA/ORA  
AEA  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
1
Read  
Pointer  
Pointer  
1K/4K/16K  
C
017  
× 36  
Dual Ported  
Memory  
CLKC  
(FIFO2)  
Port C  
Control  
Logic  
WENC  
SIZEC  
MBC  
Mail2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06026 Rev. *C  
Revised December 26, 2002  

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