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CY7C43684 PDF预览

CY7C43684

更新时间: 2024-11-24 04:53:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
39页 646K
描述
1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

CY7C43684 数据手册

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CY7C43644  
CY7C43664  
CY7C43684  
1K/4K x36 x2 Bidirectional Synchronous  
FIFO with Bus Matching  
• Fully asynchronous and simultaneous read and write  
operation permitted  
Features  
• High-speed,low-power,bidirectional,First-In,First-Out  
(FIFO) memories with bus matching capabilities  
• 1K x36 x2 (CY7C43644)  
• Mailbox bypass register for each FIFO  
• Parallel and Serial Programmable Almost-Full and  
Almost-Empty flags  
• 4K x36 x2 (CY7C43664)  
• Retransmit function  
• 16K x36 x2 (CY7C43684)  
• 0.35-micron CMOS for optimum speed/power  
• Standard or FWFT mode user selectable  
• Partial Reset  
• High-speed 133-MHz operation (7.5 ns read/write  
cycle times)  
• Low power  
— ICC = 100 mA  
— ISB = 10 mA  
• Big or Little Endian format for word or byte bus sizes  
• 128-pin TQFP packaging  
• Easily expandable in width and depth  
Logic Block Diagram  
MBF1  
CLKA  
Mail 1  
Register  
CSA  
Port A  
Control  
Logic  
CLKB  
CSB  
W/RA  
ENA  
MBA  
RT2  
1K/4K/16K  
x36  
Dual Ported  
W/RB  
Port B  
Control  
Logic  
ENB  
MBB  
Memory  
RTI  
BE  
BM  
SIZE  
MRS1  
PRS1  
FIFO1,  
Mail 1  
Reset  
Logic  
Write  
Pointer  
Read  
Pointer  
FFA/IRA  
AFA  
Status  
Flag Logic  
EFB/ORB  
AEB  
36  
SPM  
FS0/SD  
FS1/SEN  
B
035  
Timing  
Mode  
Programmable  
Flag Offset  
Registers  
BE/FWFT  
36  
A
035  
Status  
Flag Logic  
FFB/IRB  
AFB  
EFA/ORA  
AEA  
Write  
Pointer  
Read  
Pointer  
FIFO1,  
Mail 1  
Reset  
Logic  
MRS2  
PRS2  
256/512/1K  
4K/16K x36  
Dual Ported  
Memory  
Mail 2  
Register  
MBF2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06022 Rev. *B  
Revised December 26, 2002  

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