Datasheet > CY7C2565XV18-633BZC

CY7C2565XV18-633BZC

更新时间： 2024-11-06 15:17:35

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
29页	1291K
描述
Synchronous SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C2565XV18-633BZC 数据手册

浏览型号CY7C2565XV18-633BZC的Datasheet PDF文件第2页

浏览型号CY7C2565XV18-633BZC的Datasheet PDF文件第3页

浏览型号CY7C2565XV18-633BZC的Datasheet PDF文件第4页

浏览型号CY7C2565XV18-633BZC的Datasheet PDF文件第5页

浏览型号CY7C2565XV18-633BZC的Datasheet PDF文件第6页

浏览型号CY7C2565XV18-633BZC的Datasheet PDF文件第7页

CY7C2563XV18/CY7C2565XV18

72-Mbit QDR II+ Xtreme SRAM Four-Word

Burst Architecture (2.5 Cycle Read Latency) with ODT

72-Mbit QDR^®II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.5 cycles

CY7C2563XV18 – 4M × 18

■ 633 MHz clock for high bandwidth

CY7C2565XV18 – 2M × 36

■ Four-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) interfaces on both read and write ports

The CY7C2563XV18 and CY7C2565XV18 are 1.8 V

Synchronous Pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turn-around” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ Xtreme read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 18-bit

words (CY7C2563XV18), or 36-bit words (CY7C2565XV18) that

burst sequentially into or out of the device. Because data is

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turn-arounds”.

(data transferred at 1266 MHz) at 633 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

These devices have an on-die termination feature supported for

D_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate external

termination resistors, reduce cost, reduce board area, and

simplify board routing.

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

For a complete list of related documentation, click here.

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

633 MHz

633

600 MHz Unit

600

1100

1570

MHz

Maximum Operating Current

× 18

× 36

1165

1660

Cypress Semiconductor Corporation

Document Number: 001-68997 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 23, 2017

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C2565XV18-633BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C2565XV18-633BZXC	CYPRESS	获取价格	72-Mbit QDRÂ® II Xtreme SRAM Four-Word Burst
CY7C2566KV18	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-400BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-400BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-400BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-400BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-450BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-450BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-450BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2566KV18-450BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture

与CY7C2565XV18-633BZC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C2565XV18-633BZC

CY7C2565XV18-633BZC 数据手册

与CY7C2565XV18-633BZC相关器件

与CY7C2565XV18-633BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C2565XV18-633BZC

CY7C2565XV18-633BZC 数据手册

与CY7C2565XV18-633BZC相关器件

与CY7C2565XV18-633BZC相关文章

您还可以找

您在本页遇到什么问题？