Datasheet > CY7C25682KV18-450BZC

CY7C25682KV18-450BZC

更新时间： 2024-11-06 12:28:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
29页	865K
描述
72-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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CY7C25682KV18-450BZC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	15 MM X 13 MM, 1.4 MM HEIGHT, MO-216,FBGA-165
针数：	165	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.32	最长访问时间：	0.45 ns
最大时钟频率 (fCLK)：	450 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	36	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.34 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.65 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm	Base Number Matches：	1

CY7C25682KV18-450BZC 数据手册

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CY7C25682KV18

CY7C25702KV18

72-Mbit DDR II+ SRAM Two-Word Burst Architecture

(2.5 Cycle Read Latency) with ODT

72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

Configurations

■ 72-Mbit density (4 M × 18, 2 M × 36)

With Read Cycle Latency of 2.5 cycles:

CY7C25682KV18 – 4 M × 18

■ 550 MHz clock for high bandwidth

CY7C25702KV18 – 2 M × 36

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at

1100 MHz) at 550 MHz

Functional Description

The CY7C25682KV18, and CY7C25702KV18 are 1.8 V

Synchronous Pipelined SRAMs equipped with DDR II+

architecture. The DDR II+ consists of an SRAM core with

advanced synchronous peripheral circuitry. Addresses for read

and write are latched on alternate rising edges of the input (K)

clock. Write data is registered on the rising edges of both K and

K. Read data is driven on the rising edges of K and K. Each

address location is associated with two 18-bit words

(CY7C25682KV18), or 36-bit words (CY7C25702KV18) that

burst sequentially into or out of the device.

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo Clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

These devices have an On-Die Termination feature supported

for D_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

■ Synchronous internally self-timed writes

■ DDR II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ Operates similar to DDR I Device with 1 cycle read latency

when DOFF is asserted LOW

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

550 MHz

550

500 MHz

500

450 MHz

450

400 MHz Unit

400

590

750

MHz

× 18

× 36

760

700

650

970

890

820

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-66483 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 20, 2013

12 3 4 5 6 7...29

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与CY7C25682KV18-450BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C25682KV18-500BZC	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
CY7C25682KV18-550BZXC	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
CY7C25682KV18-550BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C25682KV18-550BZXI	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
CY7C25682KV18-550BZXI	INFINEON	获取价格	DDR-II+ CIO
CY7C2568KV18	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2568KV18-400BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2568KV18-400BZC	ROCHESTER	获取价格	4MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C2568KV18-400BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C2568KV18-400BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture

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