Datasheet > CY7C25

CY7C25

更新时间： 2024-11-24 06:51:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
17页	607K
描述
256/512/1K/2K/4K x 9 Asynchronous FIFO

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CY7C25 数据手册

CY7C419/21/25/29/33256/512/1K/2K/4K

x 9 Asynchronous FIFO

CY7C419/21/25/29/33

256/512/1K/2K/4K x 9 Asynchronous FIFO

Features

Functional Description

■ Asynchronous first-in first-out (FIFO) buffer memories

■ 256 x 9 (CY7C419)

The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and

CY7C432/3 are first-in first-out (FIFO) memories offered in

600-mil wide and 300-mil wide packages. There are 256, 512,

1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each

FIFO memory is organized such that the data is read in the same

sequential order that it was written. Full and empty flags are

provided to prevent overrun and underrun. Three additional pins

are also provided to facilitate unlimited expansion in width, depth,

or both. The depth expansion technique steers the control

signals from one device to another in parallel. This eliminates the

serial addition of propagation delays, so that throughput is not

reduced. Data is steered in a similar manner.

■ 512 x 9 (CY7C421)

■ 1K x 9 (CY7C425)

■ 2K x 9 (CY7C429)

■ 4K x 9 (CY7C433)

■ Dual-ported RAM cell

■ High speed 50 MHz read and write independent of depth and

width

The read and write operations may be asynchronous; each can

occur at a rate of 50 MHz. The write operation occurs when the

write (W) signal is LOW. Read occurs when read (R) goes LOW.

The nine data outputs go to the high impedance state when R is

HIGH.

■ Low operating power: I_CC= 35 mA

■ Empty and full flags (Half Full flag in standalone)

■ TTL compatible

A Half Full (HF) output flag that is valid in the standalone and

width expansion configurations is provided. In the depth

expansion configuration, this pin provides the expansion out

(XO) information that is used to tell the next FIFO that it is

activated.

■ Retransmit in standalone

■ Expandable in width

■ PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP

■ Pb-free packages available

In the standalone and width expansion configurations, a LOW on

the retransmit (RT) input causes the FIFOs to retransmit the

data. Read enable (R) and write enable (W) must both be HIGH

during retransmit, and then R is used to access the data.

■ Pin compatible and functionally equivalent to IDT7200,

IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,

AM7202, AM7203, and AM7204

The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,

CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated

using an advanced 0.65-micron P-well CMOS technology. Input

ESD protection is greater than 2000V and latch-up is prevented

by careful layout and guard rings.

Logic Block Diagram

Cypress Semiconductor Corporation

Document #: 38-06001 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 09, 2008

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与CY7C25相关器件

型号	品牌	获取价格	描述	数据表
CY7C251-45DC	CYPRESS	获取价格	OTP ROM, 16KX8, 45ns, CMOS, CDIP28, 0.300 INCH, CERDIP-28
CY7C251-45DI	CYPRESS	获取价格	OTP ROM, 16KX8, 45ns, CMOS, CDIP28, 0.300 INCH, SLIM, CERDIP-28
CY7C251-45PI	CYPRESS	获取价格	OTP ROM, 16KX8, 45ns, CMOS, PDIP28, 0.300 INCH, SLIM, PLASTIC, DIP-28
CY7C251-45WI	CYPRESS	获取价格	UVPROM, 16KX8, 45ns, CMOS, CDIP28, 0.300 INCH, WINDOWED, SLIM, CERDIP-28
CY7C251-55DC	CYPRESS	获取价格	OTP ROM, 16KX8, 55ns, CMOS, CDIP28, 0.300 INCH, CERDIP-28
CY7C251-55LMB	CYPRESS	获取价格	OTP ROM, 16KX8, 55ns, CMOS, LCC-32
CY7C251-55PI	CYPRESS	获取价格	OTP ROM, 16KX8, 55ns, CMOS, PDIP28, 0.300 INCH, SLIM, PLASTIC, DIP-28
CY7C251-55WI	CYPRESS	获取价格	UVPROM, 16KX8, 55ns, CMOS, CDIP28, 0.300 INCH, WINDOWED, SLIM, CERDIP-28
CY7C251-65DC	ETC	获取价格	x8 EPROM
CY7C251-65DI	CYPRESS	获取价格	OTP ROM, 16KX8, 65ns, CMOS, CDIP28, 0.300 INCH, SLIM, CERDIP-28

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