Datasheet > CY7C1566KV18

CY7C1566KV18

更新时间： 2024-11-23 06:51:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
28页	814K
描述
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1566KV18 数据手册

CY7C1566KV18, CY7C1577KV18

CY7C1568KV18, CY7C1570KV18

PRELIMINARY

72-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.5 Cycle Read Latency)

Features

Configurations

■ 72 Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 550 MHz clock for high bandwidth

With Read Cycle Latency of 2.5 cycles:

CY7C1566KV18 – 8M x 8

CY7C1577KV18 – 8M x 9

■ 2-word burst for reducing address bus frequency

CY7C1568KV18 – 4M x 18

CY7C1570KV18 – 2M x 36

■ Double Data Rate (DDR) interfaces

(data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

Functional Description

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

The CY7C1566KV18, CY7C1577KV18, CY7C1568KV18, and

CY7C1570KV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1566KV18), 9-bit words (CY7C1577KV18), 18-bit

words (CY7C1568KV18), or 36-bit words (CY7C1570KV18) that

burst sequentially into or out of the device.

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ DDR-II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to DDR-I device with 1 cycle read latency

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

when DOFF is asserted LOW

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

❐ Supports both 1.5V and 1.8V IO supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Phase-Locked Loop (PLL) for accurate data placement

Table 1. Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

550 MHz

500 MHz

500

450 MHz

450

400 MHz

400

Unit

MHz

550

740

760

970

690

630

580

690

630

580

x18

x36

700

650

590

890

820

750

Note

1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V

= 1.4V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-15880 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 24, 2009

[+] Feedback

12 3 4 5 6 7...28

中文翻译

下载PDF

与CY7C1566KV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1566KV18_11	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566KV18-400BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-400BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-400BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-400BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-450BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-450BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-450BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-450BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1566KV18-500BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture

与CY7C1566KV18相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

35
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

26
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

54
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

52

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1566KV18

CY7C1566KV18 数据手册

与CY7C1566KV18相关器件

与CY7C1566KV18相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1566KV18

CY7C1566KV18 数据手册

与CY7C1566KV18相关器件

与CY7C1566KV18相关文章

您还可以找

您在本页遇到什么问题？