Datasheet > CY7C1566V18-333BZC

CY7C1566V18-333BZC

更新时间： 2024-11-19 05:09:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
27页	1198K
描述
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C1566V18

CY7C1577V18

CY7C1568V18

CY7C1570V18

72-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.5 Cycle Read Latency)

Features

Functional Description

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 300 MHz to 400 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

The CY7C1566V18, CY7C1577V18, CY7C1568V18, and

CY7C1570V18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of both K and K. Each address location is associated with two

8-bit words (CY7C1566V18), 9-bit words (CY7C1577V18),

18-bit words (CY7C1568V18), or 36-bit words (CY7C1570V18)

that burst sequentially into or out of the device.

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

Asynchronous inputs include output impedance matching input

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

(ZQ). Synchronous data outputs (Q, that share the same

physical pins with the data inputs, D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from individual DDR SRAMs in the system

design.

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and Variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1566V18 – 8M x 8

CY7C1577V18 – 8M x 9

CY7C1568V18 – 4M x 18

CY7C1570V18 – 2M x 36

Selection Guide

400 MHz

400

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

1400

1300

1200

1100

x18

x36

1100

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06551 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 07, 2007

12 3 4 5 6 7...27

中文翻译

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与CY7C1566V18-333BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1566V18-333BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-333BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-333BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-375BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-375BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-375BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-375BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-400BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-400BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-400BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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