Datasheet > 存储 > SRAM> CY7C1546V18-333BZXI

CY7C1546V18-333BZXI

更新时间： 2024-11-20 05:09:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
27页	1199K
描述
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1546V18-333BZXI 数据手册

浏览型号CY7C1546V18-333BZXI的Datasheet PDF文件第2页

浏览型号CY7C1546V18-333BZXI的Datasheet PDF文件第3页

浏览型号CY7C1546V18-333BZXI的Datasheet PDF文件第4页

浏览型号CY7C1546V18-333BZXI的Datasheet PDF文件第5页

浏览型号CY7C1546V18-333BZXI的Datasheet PDF文件第6页

CY7C1546V18

CY7C1557V18

CY7C1548V18

CY7C1550V18

72-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Functional Description

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 300 MHz to 375 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

The CY7C1546V18, CY7C1557V18, CY7C1548V18, and

CY7C1550V18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of both K and K. Each address location is associated with two

8-bit words (CY7C1546V18), 9-bit words (CY7C1557V18),

18-bit words (CY7C1548V18), or 36-bit words (CY7C1550V18)

that burst sequentially into or out of the device.

■ Double Data Rate (DDR) interfaces

(data transferred at 750 MHz) at 375 MHz

■ Read latency of 2.0 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

Asynchronous inputs include output impedance matching input

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

(ZQ). Synchronous data outputs (Q, that share the same

physical pins with the data inputs, D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from individual DDR SRAMs in the system

design.

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and Variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1546V18 – 8M x 8

CY7C1557V18 – 8M x 9

CY7C1548V18 – 4M x 18

CY7C1550V18 – 2M x 36

Selection Guide

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

1300

1200

1100

x18

x36

1100

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06550 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 7, 2007

12 3 4 5 6 7...27

中文翻译

下载PDF

与CY7C1546V18-333BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1546V18-375BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1546V18-375BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1546V18-375BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1546V18-375BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18_12	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZC	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZC	INFINEON	获取价格	DDR-II+ CIO
CY7C1548KV18-400BZI	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZXC	INFINEON	获取价格	DDR-II+ CIO

与CY7C1546V18-333BZXI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

24
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

16
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

48
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1546V18-333BZXI

CY7C1546V18-333BZXI 数据手册

与CY7C1546V18-333BZXI相关器件

与CY7C1546V18-333BZXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1546V18-333BZXI

CY7C1546V18-333BZXI 数据手册

与CY7C1546V18-333BZXI相关器件

与CY7C1546V18-333BZXI相关文章

您还可以找

您在本页遇到什么问题？