Datasheet > CY7C1548KV18

CY7C1548KV18

更新时间： 2024-11-20 09:45:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
31页	927K
描述
72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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数据手册

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CY7C1548KV18 数据手册

CY7C1546KV18, CY7C1557KV18

CY7C1548KV18, CY7C1550KV18

72-Mbit DDR II+ SRAM 2-Word Burst

Architecture (2.0 Cycle Read Latency)

72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

Features

Configurations

■ 72-Mbit density (8 M × 8, 8 M × 9, 4 M × 18, 2 M × 36)

■ 450-MHz clock for high bandwidth

With Read Cycle Latency of 2.0 cycles:

CY7C1546KV18 – 8 M × 8

CY7C1557KV18 – 8 M × 9

■ 2-word burst for reducing address bus frequency

CY7C1548KV18 – 4 M × 18

CY7C1550KV18 – 2 M × 36

■ Double data rate (DDR) interfaces

(data transferred at 900 MHz) at 450 MHz

■ Available in 2.0 clock cycle latency

Functional Description

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

The CY7C1546KV18, CY7C1557KV18, CY7C1548KV18, and

CY7C1550KV18 are 1.8 V Synchronous Pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1546KV18), 9-bit words (CY7C1557KV18), 18-bit

words (CY7C1548KV18), or 36-bit words (CY7C1550KV18) that

burst sequentially into or out of the device.

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ DDR II+ operates with 2.0 cycle read latency when DOFF is

asserted HIGH

■ Operatessimilarto DDR Idevice with 1 cycle read latencywhen

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

DOFF is asserted LOW

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

■ High-speed transceiver logic (HSTL) inputs and variable drive

HSTL output buffers

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(13 ×15 ×1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-Locked Loop (PLL) for accurate Data Placement

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-15879 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 25, 2011

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与CY7C1548KV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1548KV18_12	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZC	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZC	INFINEON	获取价格	DDR-II+ CIO
CY7C1548KV18-400BZI	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C1548KV18-450BZC	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-450BZI	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548V18	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548V18-300BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548V18-300BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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