Datasheet > CY7C1546V18-375BZXI

CY7C1546V18-375BZXI

更新时间： 2024-11-24 05:09:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
27页	1199K
描述
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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技术参数
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CY7C1546V18-375BZXI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.84	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	375 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	17 mm
内存密度：	67108864 bit	内存集成电路类型：	DDR SRAM
内存宽度：	8	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	8MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.525 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	1.3 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	15 mm

CY7C1546V18-375BZXI 数据手册

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CY7C1546V18

CY7C1557V18

CY7C1548V18

CY7C1550V18

72-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Functional Description

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 300 MHz to 375 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

The CY7C1546V18, CY7C1557V18, CY7C1548V18, and

CY7C1550V18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of both K and K. Each address location is associated with two

8-bit words (CY7C1546V18), 9-bit words (CY7C1557V18),

18-bit words (CY7C1548V18), or 36-bit words (CY7C1550V18)

that burst sequentially into or out of the device.

■ Double Data Rate (DDR) interfaces

(data transferred at 750 MHz) at 375 MHz

■ Read latency of 2.0 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

Asynchronous inputs include output impedance matching input

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

(ZQ). Synchronous data outputs (Q, that share the same

physical pins with the data inputs, D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from individual DDR SRAMs in the system

design.

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and Variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1546V18 – 8M x 8

CY7C1557V18 – 8M x 9

CY7C1548V18 – 4M x 18

CY7C1550V18 – 2M x 36

Selection Guide

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

1300

1200

1100

x18

x36

1100

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06550 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 7, 2007

12 3 4 5 6 7...27

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与CY7C1546V18-375BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1548KV18	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18_12	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZC	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZC	INFINEON	获取价格	DDR-II+ CIO
CY7C1548KV18-400BZI	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-400BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C1548KV18-450BZC	CYPRESS	获取价格	72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548KV18-450BZI	CYPRESS	获取价格	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548V18	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1548V18-300BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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