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CY7C1474BV33-167BGIT PDF预览

CY7C1474BV33-167BGIT

更新时间： 2024-11-09 19:24:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
34页 845K
描述
ZBT SRAM, 1MX72, 3.4ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209

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CY7C1474BV33-167BGIT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：14 X 22 MM, 1.76 MM HEIGHT, FBGA-209Reach Compliance Code：not_compliant
风险等级：5.65最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：167 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B209
长度：22 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：72
湿度敏感等级：3功能数量：1
端子数量：209字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX72输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA209,11X19,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.96 mm
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.45 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1474BV33-167BGIT 数据手册

 浏览型号CY7C1474BV33-167BGIT的Datasheet PDF文件第2页浏览型号CY7C1474BV33-167BGIT的Datasheet PDF文件第3页浏览型号CY7C1474BV33-167BGIT的Datasheet PDF文件第4页浏览型号CY7C1474BV33-167BGIT的Datasheet PDF文件第5页浏览型号CY7C1474BV33-167BGIT的Datasheet PDF文件第6页浏览型号CY7C1474BV33-167BGIT的Datasheet PDF文件第7页 
CY7C1470BV33  
CY7C1472BV33  
CY7C1474BV33  
72-Mbit (2 M × 36/4 M × 18/1 M × 72)  
Pipelined SRAM with NoBL™ Architecture  
72-Mbit (2  
M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin-compatible and functionally equivalent to ZBT™  
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33  
are 3.3 V, 2 M × 36/4 M × 18/1 M × 72 Synchronous pipelined  
burst SRAMs with No Bus Latency™ (NoBL logic,  
respectively. They are designed to support unlimited true  
back-to-back read or write operations with no wait states. The  
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are  
equipped with the advanced (NoBL) logic required to enable  
consecutive read or write operations with data being transferred  
on every clock cycle. This feature dramatically improves the  
throughput of data in systems that require frequent read or write  
transitions. The CY7C1470BV33, CY7C1472BV33, and  
CY7C1474BV33 are pin compatible and functionally equivalent  
to ZBT devices.  
■ Supports 250 MHz bus operations with zero wait states  
❐ Available speed grades are 250, 200, and 167 MHz  
■ Internally self timed output buffer control to eliminate the need  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte Write capability  
■ Single 3.3 V power supply  
■ 3.3 V/2.5 V I/O power supply  
■ Fast clock-to-output time  
❐ 3.0 ns (for 250 MHz device)  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the Clock Enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ Clock Enable (CEN) pin to suspend operation  
■ Synchronous self timed writes  
■ CY7C1470BV33,  
CY7C1472BV33  
available  
in  
Write operations are controlled by the Byte Write Selects  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1474BV33  
available in Pb-free and non-Pb-free 209-ball FBGA package  
(BWa–BWd  
for  
CY7C1470BV33,  
BWa–BWb  
for  
CY7C1472BV33, and BWa–BWh for CY7C1474BV33) and a  
Write Enable (WE) input. All writes are conducted with on-chip  
synchronous self timed write circuitry.  
■ IEEE 1149.1 JTAG Boundary Scan compatible  
■ Burst capability – linear or interleaved burst order  
■ “ZZ” Sleep Mode option and Stop Clock option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum Access Time  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz Unit  
3.4  
450  
120  
ns  
Maximum Operating Current  
500  
500  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
Cypress Semiconductor Corporation  
Document Number: 001-15031 Rev. *M  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 20, 2014  
1234567...34

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CY7C1474BV33-167BGIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1474V33-200BGC CYPRESS

完全替代

 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

与CY7C1474BV33-167BGIT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1474BV33-167BGXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-167BGXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-200BGC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-200BGCT CYPRESS

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 		ZBT SRAM, 1MX72, 3ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
CY7C1474BV33-200BGI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-200BGXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-200BGXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-250BGC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-250BGI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV33-250BGXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

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