Datasheet > CY7C1474V25

CY7C1474V25

更新时间： 2024-09-17 21:59:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	383K
描述
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1474V25 数据手册

CY7C1470V25

CY7C1472V25

CY7C1474V25

PRELIMINARY

72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined

SRAM with NoBL™ Architecture

Functional Description

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200, and 167 MHz

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,

2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs

with No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1470V25/

CY7C1472V25/CY7C1474V25 are equipped with the

advanced (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data in systems that require frequent Write/Read transitions.

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

The

CY7C1470V25/CY7C1472V25/CY7C1474V25

are

• Single 2.5V power supply

pin-compatible and functionally equivalent to ZBT devices.

• 2.5V/1.8V I/O operation

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle. Write operations are controlled by the

Byte Write Selects (BW_a–BW_hfor CY7C1474V25, BW_a–BW_d

for CY7C1470V25 and BW_a–BW_bfor CY7C1472V25) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

• Fast clock-to-output times

— 3.0 ns (for 250-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• CY7C1470V25 and CY7C1472V25 available in lead-free

100 TQFP, and 165 fBGA packages. CY7C1474V25

available in 209-ball fBGA package.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

• Compatible with IEEE 1149.1 JTAG Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Logic Block Diagram-CY7C1470V25 (2M x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05290 Rev. *E

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised December 5, 2004

12 3 4 5 6 7...27

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与CY7C1474V25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1474V25-167BGC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-167BGC	ROCHESTER	获取价格	1MX72 ZBT SRAM, 3.4ns, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
CY7C1474V25-167BGI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-167BGXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-167BGXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-200BGC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-200BGC	INFINEON	获取价格	Synchronous SRAM
CY7C1474V25-200BGI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-200BGXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-200BGXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR

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