Datasheet > CY7C1474V25-200BX

CY7C1474V25-200BX

更新时间： 2024-09-18 20:07:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
28页	474K
描述
Application Specific SRAM, 1MX72, 3ns, CMOS, PBGA209

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CY7C1474V25-200BX 技术参数

生命周期：	Obsolete	包装说明：	BGA, BGA209,11X19,40
Reach Compliance Code：	compliant	风险等级：	5.54
最长访问时间：	3 ns	最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B209
内存密度：	75497472 bit	内存集成电路类型：	APPLICATION SPECIFIC SRAM
内存宽度：	72	端子数量：	209
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA209,11X19,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	电源：	1.8/2.5,2.5 V
认证状态：	Not Qualified	最小待机电流：	2.38 V
子类别：	SRAMs	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

CY7C1474V25-200BX 数据手册

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CY7C1470V25

CY7C1472V25

CY7C1474V25

PRELIMINARY

2M x 36/4M x 18/1M x 72 Pipelined SRAM

with NoBL™ Architecture

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

BWS_c, BWS_d, BWS_e, BWS_f, BWS_g, BWS_h), and Read-Write

control (WE). BWS_cand BWS_dapply to CY7C1470V25 and

CY7C1474V25 only. BWS_e, BWS_f, BWS_g, and BWS_happly to

CY7C1474V25 only.

Features

• Zero Bus Latency™, no dead cycles between Write and

Read cycles

• Fast clock speed: 250, 200, and 167 MHz

• Fast access time: 2.6, 3.0, and 3.4 ns

• Internally synchronized registered outputs eliminate

the need to control OE

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later its associated data

occurs, either Read or Write.

• Single 2.5V + 5%/–5%

• Separate V_DDQfor 2.5V or 1.8V I/O

• Single WE (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

Clock Enable (CEN) pin allows operation of the

CY7C1470V25, CY7C1472V25, and CY7C1474V25 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is HIGH and the internal device registers

will hold their previous values.

• Individual byte Write (BWS_a–BWS_h) control (may be

tied LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1470V25 and CY7C1472V25). 209-ball

BGA package for CY7C1474V25.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in high

impedance state two cycles after chip is deselected or a write

cycle is initiated.

• 165-ball FBGA package is offered by opportunity basis

(Please contact Cypress sales or marketing)

The CY7C1470V25, CY7C1472V25, and CY7C1474V25

have an on-chip two-bit burst counter. In the burst mode,

CY7C1470V25, CY7C1472V25, and CY7C1474V25 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH).

Functional Description

The CY7C1470V25, CY7C1472V25, and CY7C1474V25

SRAMs are designed to eliminate dead cycles when transi-

tions from Read to Write or vice versa. These SRAMs are

optimized for 100% bus utilization and achieve Zero Bus

Latency. They integrate 2,097,152 × 36/4,194,304 × 18/

1,048,576 × 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Cypress Synchronous Burst

SRAM family employs high-speed, low-power CMOS designs

using advanced single layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Cypress Semiconductor Corporation

Document #: 38-05290 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 22, 2003

12 3 4 5 6 7...28

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与CY7C1474V25-200BX相关器件

型号	品牌	获取价格	描述	数据表
CY7C1474V25-250BGC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-250BGI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-250BGXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-250BGXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1474V25-250BX	CYPRESS	获取价格	Application Specific SRAM, 1MX72, 2.6ns, CMOS, PBGA209
CY7C1474V33	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1474V33-167BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1474V33-167BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1474V33-167BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1474V33-167BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

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