Datasheet > CY7C1474BV25

CY7C1474BV25

更新时间： 2024-11-07 05:19:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	868K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1474BV25 数据手册

CY7C1470BV25

CY7C1472BV25, CY7C1474BV25

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

■ Pin-compatible and functionally equivalent to ZBT™

The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25

are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back read

or write operations with no wait states. The CY7C1470BV25,

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 167 MHz

■ Internally self-timed output buffer control to eliminate the need

CY7C1472BV25, and CY7C1474BV25 are equipped with the

advanced (NoBL) logic required to enable consecutive read or

write operations with data being transferred on every clock cycle.

This feature dramatically improves the throughput of data in

systems that require frequent read or write transitions. The

CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are

pin-compatible and functionally equivalent to ZBT devices.

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ Single 2.5V power supply

■ 2.5V IO supply (V_DDQ

)

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the Byte Write Selects

■ Fast clock-to-output times

❐ 3.0 ns (for 250-MHz device)

■ Clock Enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

(BW_a–BW_d

for

CY7C1470BV25,

BW_a–BW_b

for

■ CY7C1470BV25, CY7C1472BV25 available in

CY7C1472BV25, and BW_a–BW_hfor CY7C1474BV25) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1474BV25

available in Pb-free and non-Pb-free 209-ball FBGA package

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst capability—linear or interleaved burst order

■ “ZZ” Sleep Mode option and Stop Clock option

Selection Guide

Description

Maximum Access Time

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

3.0

450

120

Maximum Operating Current

450

400

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document #: 001-15032 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 29, 2008

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与CY7C1474BV25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1474BV25-167BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-167BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-167BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-167BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-200BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-200BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-200BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-200BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-250BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-250BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

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