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CY7C1464AV33-167BGI

更新时间： 2024-11-16 05:09:35
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赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
27页 509K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
36-Mbit (1M x 36/2M x 18/512K x 72)  
Pipelined SRAM with NoBL™ Architecture  
Functional Description  
Features  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200 and 167 MHz  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are  
3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.  
They are designed to support unlimited true back-to-back  
Read/Write operations with no wait states. The  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33  
are  
equipped with the advanced (NoBL) logic required to enable  
consecutive Read/Write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data in systems that require frequent  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
Write/Read  
transitions.  
The  
• 3.3V power supply  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin  
compatible and functionally equivalent to ZBT devices.  
• 3.3V/2.5V I/O power supply  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
• CY7C1460AV33, CY7C1462AV33 available in  
JEDEC-standard lead-free 100-pin TQFP, lead-free and  
non-lead-free 165-ball FBGA package. CY7C1464AV33  
available in lead-free and non-lead-free 209-ball FBGA  
package  
Write operations are controlled by the Byte Write Selects  
(BWa–BWh  
CY7C1460AV33 and BWa–BWb for CY7C1462AV33) and a  
Write Enable (WE) input. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
for  
CY7C1464AV33,  
BWa–BWd  
for  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram-CY7C1460AV33 (1M x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05353 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 22, 2006  
[+] Feedback  
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