Datasheet > CY7C144AV_12

CY7C144AV_12

更新时间： 2022-05-13 19:37:16

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
21页	557K
描述
3.3 V 8 K / 16 K Ã 8 Asynchronous Dual-Port Static RAM

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数据手册

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CY7C144AV_12 数据手册

CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3

Asynchronous Dual-Port Static RAM

V 8 K / 16 K × 8

CY7C144AV

CY7C006AV

3.3 V 8 K / 16 K × 8

Asynchronous Dual-Port Static RAM

3.3

V 8 K / 16 K × 8 Dual-Port Static RAM

■ Automatic power-down

Features

■ Expandable data bus to 16 bits or more using Master/ Slave

chip select when using more than one device

■ True dual-ported memory cells which allow simultaneous

access of the same memory location

■ On-chip arbitration logic

■ 8 K / 16 K × 8 organizations (CY7C144AV/CY7C006AV)

■ Semaphores included to permit software handshaking

between ports

■ 0.35-micron complementary metal oxide semiconductor

(CMOS) for optimum speed/power

■ INT flag for port-to-port communication

■ Pin select for Master or Slave

■ High-speed access: 25 ns

■ Low operating power

■ Available in 64-pin thin quad flat pack (TQFP) (7C006AV and

7C144AV)

❐ Active: I_CC= 115 mA (typical)

❐ Standby: I_SB3= 10 A (typical)

■ Pb-free packages available

■ Fully asynchronous operation

Logic Block Diagram

R/W_L

R/W_R

CE_R

CE_L

OE_L

OE_R

[1]

I/O_0L–I/O_7L

I/O_0R–I/O_7R

I/O

Control

I/O

Control

13–14

[2]

Address

Decode

Address

Decode

[2]

True Dual-Ported

RAM Array

A_0L–A_12–13L

A_0R–A_12–13R

13–14

[2]

A_0L–A_12–13L

A_0R–A_12–13R

CE_R

CE_L

Interrupt

Semaphore

Arbitration

OE_L

OE_R

R/W_L

SEM_L

R/W_R

SEM_R

BUSY_R^[3]

INT_R

BUSY_L^[3]

INT_L

M/S

Notes

1. I/O –I/O for × 8 devices

2. A –A for 8K devices; A –A for 16K devices

3. BUSY is an output in master mode and an input in slave mode.

Cypress Semiconductor Corporation

Document Number: 38-06051 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 1, 2012

12 3 4 5 6 7...21

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