Datasheet > CY7C1443V25-150BGC

CY7C1443V25-150BGC

更新时间： 2024-11-30 05:13:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	988K
描述
Standard SRAM, 2MX18, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1443V25-150BGC 数据手册

浏览型号CY7C1443V25-150BGC的Datasheet PDF文件第2页

浏览型号CY7C1443V25-150BGC的Datasheet PDF文件第3页

浏览型号CY7C1443V25-150BGC的Datasheet PDF文件第4页

浏览型号CY7C1443V25-150BGC的Datasheet PDF文件第5页

浏览型号CY7C1443V25-150BGC的Datasheet PDF文件第6页

浏览型号CY7C1443V25-150BGC的Datasheet PDF文件第7页

CY7C1447V25

CY7C1443V25

CY7C1441V25

PRELIMINARY

1M x 36/2M x 18/512K x 72 Flow-Thru SRAM

inputs are gated by registers controlled by a positive-

edge-triggered clock input (CLK). The synchronous inputs

Features

•Supports 133-MHz bus operations

•1M x 36/2M x18/512K x 72 common I/O

•Fast clock-to-output times

— 5.5 ns (for 150-MHz device)

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

include all addresses, all data inputs, address-pipelining Chip

Enable (CE), Burst Control Inputs (ADSC, ADSP, and ADV),

Write Enables (BWa, BWb, BWc, BWd,BWe,BW_f,BW_gand

BW_h, BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

• Single 2.5V –5% and +5% power supply V_DD

• Separate V_DDQfor 2.5V or 1.8V I/O

• Byte Write Enable and Global Write control

• Burst capability–linear or interleaved burst order

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or address status controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

• Automatic power down available using ZZ mode or CE

deselect

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA, 165-ball FBGA, and

100-pin TQFP packages (CY7C1441V25 and

CY7C1443V25). 209 FBGA package for CY7C1447V25.

Address, data inputs, and Write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the Write control inputs.

Individual byte Write allows individual byte to be written. BWa

controls DQ1–DQ8 and DP1. BWb controls DQ9–DQ16 and

DP2. BWc controls DQ17–DQ24and DP3. BWd controls

DQ25–DQ32 and DP4. BWe controls DQ33–DQ40 and DP5.

BWf controls DQ41–DQ48 and DP6. BWg controls

DQ49–DQ56 and DP7. BWh controls DQ57–DQ64 and DP8.

BWa, BWb BWc, BWd, BWe, BWf, BWg, and BWh can be

active only with BWE LOW. GW LOW causes all bytes to be

written. Write pass-thru capability allows written data available

at the output for the immediately next Read cycle. This device

also incorporates pipelined enable circuit for easy depth

expansion without penalizing system performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1441V25/CY7C1443V25/CY7C1447V25 SRAMs

integrate 1,048,576 × 36/2,097,152 × 18/524,288 × 72 SRAM

cells with advanced synchronous peripheral circuitry and a

two-bit counter for internal burst operation. All synchronous

All inputs and outputs of the CY7C1441V25/ CY7C1443V25/

CY7C1447V25 are JEDEC-standard JESD8-5 compatible.

MODE

Logic Block Diagram

(A_[1;0]

)

CY7C1441V25–1M × 36

CLK

BURST

COUNTER

ADV

CLR

ADSC

ADSP

ADDRESS

1M × 36

Memory

Array

A_[19:0]

DQ_d, DP_d

BYTEWRITE

REGISTERS

BWE

DQ_c, DP_c

BYTEWRITE

REGISTERS

DQ_b, DP_b

BYTEWRITE

REGISTERS

DQ_a, DP_a

BYTEWRITE

REGISTERS

ENABLE CE

OUTPUT

REGISTERS

CLK

INPUT

REGISTERS

CLK

ENABLE DELAY

SLEEP

CONTROL

DQ_a,b,c,d

DP_a,b,c,d

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05186 Rev. **

Revised April 19, 2002

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1443V25-150BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1443V25-150BZC	CYPRESS	获取价格	Standard SRAM, 2MX18, 5.5ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165
CY7C1443V33-117AC	CYPRESS	获取价格	Standard SRAM, 2MX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1443V33-150AC	CYPRESS	获取价格	Standard SRAM, 2MX18, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1444AV25	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
CY7C1444AV25-167AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
CY7C1444AV25-167AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
CY7C1444AV25-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
CY7C1444AV25-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
CY7C1444AV25-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
CY7C1444AV25-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM

与CY7C1443V25-150BGC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

38
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

63

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1443V25-150BGC

CY7C1443V25-150BGC 数据手册

与CY7C1443V25-150BGC相关器件

与CY7C1443V25-150BGC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1443V25-150BGC

CY7C1443V25-150BGC 数据手册

与CY7C1443V25-150BGC相关器件

与CY7C1443V25-150BGC相关文章

您还可以找

您在本页遇到什么问题？