Datasheet > 存储 > SRAM> CY7C1444AV33-167AXI

CY7C1444AV33-167AXI

更新时间： 2024-11-27 05:19:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
26页	475K
描述
36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM

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CY7C1444AV33-167AXI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.83	Is Samacsys：	N
最长访问时间：	3.4 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	167 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e4
长度：	20 mm	内存密度：	37748736 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最小待机电流：	3.14 V	子类别：	SRAMs
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	14 mm
Base Number Matches：	1

CY7C1444AV33-167AXI 数据手册

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CY7C1444AV33

CY7C1445AV33

36-Mbit (1M x 36/2Mx 18) Pipelined

DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1444AV33/CY7C1445AV33 SRAM integrates 1M x

36/2M x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

• Depth expansion without wait state

• 3.3V core power supply

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth- expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP,

and ADV), Write Enables (BW_X, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle. This part supports Byte

Write operations (see Pin Descriptions and Truth Table for

further details). Write cycles can be one to four bytes wide as

• Asynchronous output enable

• CY7C1444AV33, CY7C1445AV33 available in

JEDEC-standard lead-free 100-pin TQFP package and

lead-free and non-lead-free 165-ball FBGA package

controlled by the byte write control inputs. GW

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1444AV33/CY7C1445AV33 operates from a +3.3V

core power supply while all outputs operate with a +3.3V or a

+2.5V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

2.6

200 MHz

3.2

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

475

120

425

375

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05352 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2006

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与CY7C1444AV33-167AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1444AV33-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200AXCT	CYPRESS	获取价格	Cache SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1444AV33-200AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM

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