Datasheet > 存储 > SRAM> CY7C1444AV25-250BZXI

CY7C1444AV25-250BZXI

更新时间： 2024-11-27 05:19:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
26页	434K
描述
36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM

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CY7C1444AV25-250BZXI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	最长访问时间：	2.6 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	17 mm
内存密度：	37748736 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	1MX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	1.8/2.5,2.5 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最小待机电流：	2.38 V
子类别：	SRAMs	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	15 mm	Base Number Matches：	1

CY7C1444AV25-250BZXI 数据手册

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CY7C1444AV25

CY7C1445AV25

36-Mbit (1M x 36/2M x 18) Pipelined

DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1444AV25/CY7C1445AV25 SRAM integrates 1M x

36/2M x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

• Depth expansion without wait state

• 2.5V core power supply

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth- expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP,

and ADV), Write Enables (BW_X, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• 2.5V/1.8V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• Asynchronous output enable

• CY7C1444AV25, CY7C1445AV25 available in

JEDEC-standard lead-free 100-pin TQFP package,

lead-free and non-lead-free 165-ball FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1444AV25/CY7C1445AV25 operates from a +2.5V

core power supply while all outputs operate with a +2.5V or

1.8V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

2.6

200 MHz

3.2

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

435

120

385

335

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05351 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2006

12 3 4 5 6 7...26

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与CY7C1444AV25-250BZXI相关器件

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CY7C1444AV33	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33_10	CYPRESS	获取价格	36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Syn
CY7C1444AV33_1105	CYPRESS	获取价格	36-Mbit (1 M x 36/2 M x 18) Pipelined DCD Sync SRAM
CY7C1444AV33_12	CYPRESS	获取价格	36-Mbit (1 M Ã 36) Pipelined DCD Sync SRAM
CY7C1444AV33-167AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167AXCT	CYPRESS	获取价格	Cache SRAM, 1MX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1444AV33-167AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM

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