Datasheet > CY7C1444AV33_12

CY7C1444AV33_12

更新时间： 2024-11-27 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
23页	603K
描述
36-Mbit (1 M Ã 36) Pipelined DCD Sync SRAM

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CY7C1444AV33_12 数据手册

CY7C1444AV33

36-Mbit (1 M × 36) Pipelined DCD Sync

SRAM

36-Mbit (1

M × 36) Pipelined DCD Sync SRAM

Features

Functional Description

■ Supports bus operation up to 167 MHz

■ Available speed grade is 167 MHz

■ Registered inputs and outputs for pipelined operation

■ Optimal for performance (double-cycle deselect)

■ Depth expansion without wait state

■ 3.3 V core power supply

The CY7C1444AV33 SRAM integrates 1 M × 36 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered clock

input (CLK). The synchronous inputs include all addresses, all

data inputs, address-pipelining chip enable (CE₁),

depth-expansion chip enables (CE₂and CE₃), burst control

inputs (ADSC, ADSP, and ADV), write enables (BW_X, and BWE),

and global write (GW). Asynchronous inputs include the output

enable (OE) and the ZZ pin.

■ 2.5 V/3.3 V I/O power supply

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

■ Fast clock-to-output times

❐ 3.4 ns (for 167-MHz device)

■ Provide high-performance 3-1-1-1 access rate

■ User-selectable burst counter supporting Intel^Pentium^

interleaved or linear burst sequences

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle. This part supports byte write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as controlled

■ Separate processor and controller address strobes

■ Synchronous self-timed writes

by the byte write control inputs. GW

active

causes all bytes

LOW

This device incorporates an additional pipelined

to be written.

■ Asynchronous output enable

enable register which delays turning off the output buffers an

additional cycle when a deselect is executed. This feature allows

depth expansion without penalizing system performance.

■ CY7C1444AV33 available in JEDEC-standard Pb-free 100-pin

TQFP package

The CY7C1444AV33 operates from a +3.3 V core power supply

while all outputs operate with a +3.3 V or a +2.5 V supply. All

inputs and outputs are JEDEC-standard JESD8-5-compatible.

■ “ZZ” sleep mode option

Selection Guide

Description

Maximum access time

167 MHz Unit

3.4

375

120

Maximum operating current

Maximum CMOS standby current

Cypress Semiconductor Corporation

Document Number: 38-05352 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 14, 2012

12 3 4 5 6 7...23

中文翻译

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与CY7C1444AV33_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1444AV33-167AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167AXCT	CYPRESS	获取价格	Cache SRAM, 1MX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1444AV33-167AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200AXCT	CYPRESS	获取价格	Cache SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1444AV33-200AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM

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