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CY7C1444AV33-200BZC

更新时间： 2024-11-27 05:19:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	475K
描述
36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM

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CY7C1444AV33

CY7C1445AV33

36-Mbit (1M x 36/2Mx 18) Pipelined

DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1444AV33/CY7C1445AV33 SRAM integrates 1M x

36/2M x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

• Depth expansion without wait state

• 3.3V core power supply

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth- expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP,

and ADV), Write Enables (BW_X, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle. This part supports Byte

Write operations (see Pin Descriptions and Truth Table for

further details). Write cycles can be one to four bytes wide as

• Asynchronous output enable

• CY7C1444AV33, CY7C1445AV33 available in

JEDEC-standard lead-free 100-pin TQFP package and

lead-free and non-lead-free 165-ball FBGA package

controlled by the byte write control inputs. GW

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1444AV33/CY7C1445AV33 operates from a +3.3V

core power supply while all outputs operate with a +3.3V or a

+2.5V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

2.6

200 MHz

3.2

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

475

120

425

375

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05352 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2006

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与CY7C1444AV33-200BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1444AV33-200BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-200BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-250AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-250AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-250BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-250BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-250BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444AV33-250BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM
CY7C1444KV33	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined DCD Syn

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