Datasheet > 存储 > SRAM> CY7C1418JV18-300BZI

CY7C1418JV18-300BZI

更新时间： 2024-11-06 03:11:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器双倍数据速率时钟
页数	文件大小	规格书
26页	630K
描述
36-Mbit DDR-II SRAM 2-Word Burst Architecture

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技术参数
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CY7C1418JV18-300BZI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	17 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.88	Is Samacsys：	N
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	300 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	37748736 bit
内存集成电路类型：	DDR SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.355 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.975 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead/Silver (Sn/Pb/Ag)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	15 mm	Base Number Matches：	1

CY7C1418JV18-300BZI 数据手册

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CY7C1416JV18, CY7C1427JV18

CY7C1418JV18, CY7C1420JV18

36-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz clock for high bandwidth

The CY7C1416JV18, CY7C1427JV18, CY7C1418JV18 and

CY7C1420JV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K. Read data is

driven on the rising edges of C and C if provided, or on the rising

edge of K and K if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1416JV18

and two 9-bit words in the case of CY7C1427JV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1416JV18 and

CY7C1427JV18. On CY7C1418JV18 and CY7C1420JV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1418JV18 and two 36-bit words in the case of

CY7C1420JV18 sequentially into or out of the device.

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz for DDR-II

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when DLL is

enabled

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates like a DDR-I device with 1 cycle read latency in DLL

off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V_DD

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both in Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1416JV18 – 4M x 8

CY7C1427JV18 – 4M x 9

CY7C1418JV18 – 2M x 18

CY7C1420JV18 – 1M x 36

Selection Guide

Description

Maximum Operating Frequency

300 MHz

300

Unit

MHz

Maximum Operating Current

930

x18

x36

975

1010

Cypress Semiconductor Corporation

Document Number: 001-12558 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 10, 2008

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与CY7C1418JV18-300BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1418JV18-300BZXC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418JV18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418KV18	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1418KV18_12	CYPRESS	获取价格	36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1418KV18-250BZC	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1418KV18-250BZC	INFINEON	获取价格	DDR-II CIO
CY7C1418KV18-250BZCT	CYPRESS	获取价格	Standard SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1418KV18-250BZCT	INFINEON	获取价格	DDR-II CIO
CY7C1418KV18-250BZI	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1418KV18-250BZI	INFINEON	获取价格	DDR-II CIO

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