Datasheet > CY7C1418KV18-250BZCT

CY7C1418KV18-250BZCT

更新时间： 2024-09-17 14:56:03

品牌	Logo	应用领域
英飞凌 - INFINEON		双倍数据速率
页数	文件大小	规格书
32页	777K
描述
DDR-II CIO

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CY7C1418KV18/CY7C1420KV18

36-Mbit DDR II SRAM Two-Word

Burst Architecture

36-Mbit DDR II SRAM Two-Word Burst Architecture

Features

Configurations

■ 36-Mbit density (2M × 18, 1M × 36)

CY7C1418KV18 – 2M × 18

CY7C1420KV18 – 1M × 36

■ 333 MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) interfaces (data transferred at

666 MHz) at 333 MHz

The CY7C1418KV18, and CY7C1420KV18 are 1.8

synchronous pipelined SRAM equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced

synchronous peripheral circuitry and a 1-bit burst counter.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of C and C if provided, or on the rising edge of K and K if C/C are

not provided. On CY7C1418KV18 and CY7C1420KV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1418KV18 and two 36-bit words in the case of

CY7C1420KV18 sequentially into or out of the device.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Synchronous internally self-timed writes

■ DDR II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates similar to DDR-I device with 1 cycle read latency

when DOFF is asserted LOW

■ 1.8 V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4 V to V_DD

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

❐ Supports both 1.5 V and 1.8 V IO supply

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

For a complete list of related documentation, click here.

■ Phase locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

333 MHz

333

300 MHz

300

250 MHz Unit

250

430

490

MHz

Maximum operating current

× 18

× 36

490

460

600

560

Cypress Semiconductor Corporation

Document Number: 001-57827 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 3, 2018

12 3 4 5 6 7...32

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与CY7C1418KV18-250BZCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1418KV18-250BZI	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1418KV18-250BZI	INFINEON	获取价格	DDR-II CIO
CY7C1418KV18-250BZXC	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1418KV18-250BZXC	INFINEON	获取价格	DDR-II CIO
CY7C1418KV18-250BZXI	CYPRESS	获取价格	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1418KV18-250BZXI	INFINEON	获取价格	DDR-II CIO
CY7C1418KV18-300BZC	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1418KV18-300BZXC	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1418KV18-300BZXC	INFINEON	获取价格	DDR-II CIO
CY7C1418KV18-333BZC	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture

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